November 1992
Revised February 2005
7
4VH
C04
Hex
Inve
rte
r
74VHC04
Hex Inverter
General Description
The VHC04 is an advanced high speed CMOS Inverter
fabricated with silicon gate CMOS technology. It achieves
the high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The internal circuit is composed of 3 stages including buffer
output, which provide high noise immunity and stable out-
put. An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
■
High Speed: t
PD
3.8 ns (typ) at V
CC
5V
■
High noise immunity: V
NIH
V
NIL
28% V
CC
(Min)
■
Power down protection is provided on all inputs
■
Low Noise: V
OLP
0.4V (typ)
■
Low power dissipation: I
CC
2
P
A (Max) @ T
A
25
q
C
■
Pin and function compatible with 74HC04
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Order Number
Package
Package Description
Number
74VHC04M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC04MX_NL
(Note 1)
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC04SJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC04MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC04MTCX_NL
(Note 1)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHC04N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com
2
7
4
VH
C04
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
Pin Names
Description
A
n
Inputs
O
n
Outputs
A
O
L
H
H
L
94
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