ADV7320/ADV7321
Rev. 0 | Page 18 of 88
Pin No.
Mnemonic
Input/Output Description
62–58,
55–51
S9 to S0
I
SD or Progressive Scan/HDTV Input Port for Cr[Red/V] Data in 4:4:4 Input Mode. LSB is set up
on Pin S0. For 8-bit data input, LSB is set up on S2.
33
RESET
I
This input resets the on-chip timing generator and sets the ADV7320/ADV7321 into default
register setting. RESET is an active low signal.
47, 35
R
SET1
, R
SET2
I
A 3040 Ω resistor must be connected from this pin to AGND and is used to control the
amplitudes of the DAC outputs.
22
SCLK
I
I
2
C Port Serial Interface Clock Input.
21
SDA
I/O
I
2
C Port Serial Data Input/Output.
20
ALSB
I
TTL Address Input. This signal sets up the LSB of the I
2
C address. When this pin is tied low, the
I
2
C filter is activated, which reduces noise on the I
2
C interface.
1 V
DD_IO
P
Power Supply for Digital Inputs and Outputs.
10, 56
V
DD
P
Digital Power Supply.
41 V
AA
P
Analog Power Supply.
46 V
REF
I/O
Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
34
EXT_LF
I
External Loop Filter for the Internal PLL.
31
RTC_SCR_TR I
Multifunctional Input. Real-time control (RTC) input, timing reset input, subcarrier reset input.
19 I
2
C
I
This input pin must be tied high (V
DD_IO
) for the ADV7320/ADV7321 to interface over the I
2
C port.
64
GND_IO
Digital Input/Output Ground.
88
DVD48
harman/kardon
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