Internal Block Diagram
Figure 1.1 shows a block diagram.
Port 8
P8
7
P8
6
/FTID
P8
5
/FTIC
P8
4
/FTIB
P8
3
/FTIA
P8
2
/FTOB
P8
1
/FTOA
P8
0
/FTCI
ROM
Port 7
P7
7
P7
6
/TMOV
P7
5
/TMCIV
P7
4
/TMRIV
P7
3
Port 6
P6
7
P6
6
P6
5
P6
4
P6
3
P6
2
P6
1
P6
0
CMOS large-
current port
I
OL
= 10 mA
@V
OL
= 1V
P5
7
/
INT
7
P5
6
/
INT
6
/TMIB
P5
5
/
INT
5
/
ADTRG
P5
4
/
INT
4
P5
3
/
INT
3
P5
2
/
INT
2
P5
1
/
INT
1
P5
0
/
INT
0
Port 1
P1
0
/TMOW
P1
4
/PWM
P1
5
/
IRQ
1
P1
6
/
IRQ
2
P1
7
/
IRQ
3
/TRGV
Port 2
P2
0
/SCK
3
P2
1
/RXD
P2
2
/TXD
Port 3
P3
0
/SCK
1
P3
1
/SI
1
P3
2
/SO
1
P9
0
/FV
PP
*
P9
1
P9
2
P9
3
P9
4
Port 9
PB
0
/AN
0
PB
1
/AN
1
PB
2
/AN
2
PB
3
/AN
3
PB
4
/AN
4
PB
5
/AN
5
PB
6
/AN
6
PB
7
/AN
7
V
SS
V
CC
RES
IRQ
0
TEST
OSC
1
OSC
2
X
1
X
2
CPU
H8/300L
Data bus (lower)
System clock
generator
Subclock generator
RAM
Timer A
SCI1
Timer B1
Watchdog
timer
A/D converter
SCI3
Timer X
Timer V
14-bit PWM
AV
CC
AV
SS
Port 5
Port B
Data bus (upper)
Address bus
Figure 1.1 Block Diagram
FL8380
56
Summary of Contents for FL 8380
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