MN662790RAS1
Block Diagram
SERVO CPU
OUTPUT
PORT
MICROCOMPUTER
INTERFACE
DSL•PLL VCO
60
57
4
5
18
71
32
RST
TEST
FE
33
TE
34
RFENV
37
TRCRS
35
VDET
39
BDO
38
RFDET
36
OFT
DIGITAL
DEEMPHASIS
1 BIT DAC
LOGICS
8 TIMES
OVER SAMPLING
DIGITAL FILTER
EFM DEMODULATION
SYNC INTERPOLATION
SUBCODE DEMODULATION
CLV
SERVO
INTERPOLATION
SOFT MUTING
DIGITAL
ATTENUATION
PEAK DETECT
AUTO CUE
DIGITAL
AUDIO
INTERFACE
CIRC ERROR CORRECTION
DEINTERLEAVE
16K
SRAM
D/A
CONVERTER
29
V
REF
25
61
ECS
BYTCK/TRVSTOP
LDON
PLAY
FLOCK
TLOCK
40
42
11
12
26
KICK
21
TRV
16
DMUTE
1
BCLK
3
SRDATA
2
LRCK
23
PC
24
ECM
6
TX
64
IPFLAG
65
FLAG
22
TVD
27
TRD
28
FOD
31
TBAL
30
FBAL
43
WVEL
10
SENSE
STAT
X1
X2
MSEL
CSEL
PMCK
FCLK
SMCK
VCOF2
58
79
77
59
20
63
19
CK384/EFM
54
VCOF
49
MDATA
8
MCLK
7
MLD
9
17
44
46
45
47
41
52
76
78
RSEL
ARF
PSEL
DSLF
PLLF2
48
PLLF
62
13
67
66
55
56
68
15
14
80
CLDCK
BLKCK
SUBC
SBCK
FLAG6/RESY
69
DEMPH
CRC
CLVS
70
IOSEL
SRDATEIN/PSEL
BCLKIN/SSEL
LRCKIN/MSEL
EFM
53
PCK
SUBQ
SQCK
SSEL
I
REF
DRF
75
73
PWM
(L
)
PWM
(R
)
+
–
+
–
SUBCODE
BUFFER
51
50
AV
DD2
AV
SS2
OUTR
OUTL
74
72
A/D CONVERTER
INPUT PORT
SERVO
TIMING GENERATOR
TIMING
GENERATOR
PITCH CONTROL
VCO
V
DD
V
SS
DV
DD1
DV
SS1
AV
DD1
AV
SS1
FL8380
17
Summary of Contents for FL 8380
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Page 38: ...Motor driver IC BA6209 BA6209N Measurement circuit FL8380 38 ...
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