Internal Block Diagram
+
−
+
−
+
−
+
−
+
−
10k
Level
shift
Regulator
Mute
TSD
+
−
Level
shift
Level
shift
Level
shift
−
+
10k
10k
10k
10k
10k
10k
10k
10k
−
−
+
+
50k
10k
50
k
1
2
3
4
5
6
8
9
10
11
12
13
7
14
DO1.
1
DO1.
2
DI
1.
1
DI
1.
2
REG
REO
MUTE
GND1
DI
2.
1
DI
2.
2
DO2.
1
DO2.
2
GND2
OPOUT
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND3
DO4.
2
DO4.
1
DI
4
.2
DI
4
.1
VREF
VCC2
VCC1
DI
3
.2
DI
3
.1
DO3.
2
DO3.
1
O
P
IN
(
−
)
OPI
N
(+
)
+
−
+
−
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DO1.
1
DO1.
2
DI
1.
1
DI
1.
2
REG
REO
MUTE
GND1
DI
2.
1
DI
2.
2
DO2.
1
DO2.
2
GND2
OPOUT
GND
3
DO
4.
2
DO
4.
2
DI
4
.2
DI
4
.1
VR
E
F
V
CC2
V
CC1
DI
3
.2
DI
3
.1
DO
3.
2
DO
3.
1
OP
IN
(
+
)
OP
IN
(
−
)
FIN
(GND)
FIN
(GND)
KA9258D
FL8550
37
Summary of Contents for FL 8550
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