Block diagram
1010
A
F
TEDS
IEPE
Current
Charge
Strain
RTD
Thermo
F
(x)
T
Channel &
Card Trigger
Sample Rate
selection & Digital Filter
Channel 1 to 8/16
Communication
& Memory &
Recording control
Synchronization
& Sample Rate
Real-Time
Calculator
Event Timer
Counter
Input & Output
500 or 512 kS/s
Backplane
System Trigger Bus
Acquisition Control
Event/Timer/Counter
Master Time Base
/
/
Amplifier
Sigma Delta
ADC
Isolation
F
n
-1
n
-1
z
-1
z
-1
Σ
a
1
a
2
b
2
b
1
x
(n)
y
(n)
A
Communication and
Fast Data Streaming
500 or 512 kS/s
Sample Rate
Figure A.204:
Block Diagram
Note The typical and maximum specification given in this data sheet are based on respectively 1 σ (68.27%) and
5 σ (99.9999%) statistical evaluations of calibration results. Cards exceeding the maximum specifications are
not released for sale. All specifications are defined at 23 °C
±
2 °C, unless specified differently.
The specifications listed are valid for cards that have been calibrated and are used in the same mainframe and
slots as they were at the time of calibration. When the card is removed from its original location and placed in
another slot and/or mainframe, the Offset error, Gain error and MSE specifications are expected to increase
(up to double the original specification) due to thermal differences within the configurations.
GEN3i
636
I3763-3.1 en HBM: public
