Device Connections and Switches
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PC Cards cifX PCI, PCIe, Low Profile PCIe | Installation, Operation and Hardware Description
DOC120204UM36EN | Revision 36 | English | 2012-10 | Released | Public
© Hilscher, 2008-2012
9.9.3
Items on Hardware
Item
Explanation
SYNC Signal
3,3 V (LVTTL), maximum load 6 mA
Connector
SYNC connector, X51 (for the PC Cards cifX, as indicated under section
Pin Assignment SYNC
Connector, X51
on page 93.)
Female connector, 3 pin, pitch spacing 1.25 mm (for example, the type Molex series 51021)
and female crimp contacts in design (e. g. type Molex series 50079/50058)
SYNC connector, J3 (for CIFX 100EH-RE\CUBE)
Male Connector with jumper, 3 pin, pitch spacing 2,54 mm
Max. Cable
Length
Recommendation: Max. 50 mm
Note
: Take EMC into consideration for the cable laying
Table 82: SYNC Connector: SYNC Signal, Connector, Max. Cable Length
9.9.4
Items on Firmware
The firmware determines the input signal or output signal. The following
table shows the meaning of the SYNC signals for each protocol.
Protocol
Signal IO_SYNC0
Input/Output
Signal IO_SYNC1
Input/Output
From
Firmware
Version
Remarks
EtherCAT Slave
SYNC 0
Output
SYNC 1
Output
- Configurable
sercos Master
External trigger to start bus
cycle
Input
Rising edge
- 2.0.8.0
-
sercos Slave
CON_CLK
Output
DIV_CLK
Output
3.0.10.0
Configurable
Table 83: Meaning of the SYNC Signals for each Protocol