7
Standard Event Status Enable Register (SESER)
Setting any bit of the Standard Event Status Enable Register to 1 enables access to the corresponding bit of the
Standard Event Status Register.
Standard Event Status Register (SESR) and Standard Event Status Enable Register (SESER)
Status Byte Register (STB)
bit6
bit5
bit4
MSS ESB
MAV
Standard Event Status Register (SESR)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PON URQ CME EXE DDE QYE RQC OPC
↓
↓
↓
↓
↓
↓
↓
↓
Logical sum
←
&
&
&
&
&
&
&
&
↑
↑
↑
↑
↑
↑
↑
↑
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PON URQ CME EXE DDE QYE RQC OPC
Standard Event Status Enable Register (SESER)
Device-Specific Event Status Registers (DESR)
This instrument provides two Event Status Registers for controlling events. Each event register is an 8-bit register.
When any bit in one of these Event Status Registers enabled by its corresponding Event Status Enable Register is
set to 1, Status Byte Register, bit 3 (DSB) is set to 1.
Event Status Registers are cleared in the following situations:
• When a
*
CLS
command is executed
• When an Event Status Register query (
:DSR?
) is executed
• When the instrument is powered on
Device Event Status Register (DESR)
Bit 7
Unused
Bit 6
Unused
Bit 5
BOV
Measured data buffer overflow
Set when data is lost due to overflow of the measured data buffer.
Reset by reading this register.
Bit 4
BFL
Measure data buffer full
Set when the measured data buffer becomes full.
Reset when the buffer becomes empty.
Bit 3
STP
Measurement stop event
Set by one of the following factors:
The [STOP] key is pressed.
The interlock function was activated.
STOP was input by the handler interface.
Reset by reading this register.
Bit 2
ITL
Interlock state
Set when the interlock function is activated and start is disabled
Reset when start is enabled.
Bit 1
LM2
Reserved bit
Bit 0
LM1
Reserved bit
Summary of Contents for Super megohm SM7110
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