3.1 Tristate recognition through permanent high
11
3 Tristate recognition
OZD 485 G12(-1300) PRO Version 04 12/2014
3 Tristate recognition
3.1 Tristate recognition through permanent high
Fig. 5: Tristate recognition through permanent high
Data
K 1
R
R
PD
R
PU
R
R
PD
R
PU
typ. 220
Ω
typ. 390
Ω
typ. 390
Ω
RT+
RT±
K1±
K1+
Port 1
K 1
K 2
Port 3
Port 2
R
R
PD
R
PU
R
R
PD
R
PU
typ. 220
Ω
typ. 390
Ω
typ. 390
Ω
RT+
RT±
K1±
K1+
Port 1
K 1
K 2
Port 3
Port 2
Data
K 1
One 2-wire lead , terminated by a characteristic impe-
dence and additional pull-up/pull-down resistors, is
replaced (e.g. Modbus RTU/ASCII).
During the idle phase, a logical high level (positive volt -
age between terminals K1+ and K1-) is available. As
soon as a con stant high level is available for 2.5 µs,
the repeaters identify this as tristate and switch their
transmitters to the idle state (transmitter set to high-
resist ance).
A downward slope is identified as the start bit.
Transmission is made in the appropriate direction .
The opposite direction is disabled.
The type of tristate recognition depends on the termi nation
of the bus system used. See also chapter 5.7, page 25.
