25
MUTE 2 OUTPUT CONNECTION
•
Pin 2
is used to switch the ASW amplifier into standby (LOW) or operating mode (HIGH). This pin is also used to step
down the +16V supply at the rear of the TV to mute an optional console/speaker system connected to the +16V phono
connector, when power is removed from the TV.
COMPRESS OUTPUT CONNECTION
•
Pin 3
is the compress relay enable (HIGH) or disable (LOW) control. This output is high when a wide-screen TV is in 4:3
aspect ratio, and is low in all other modes. In 4:3 mode, black side panels are observed either side the central picture.
EXTERNAL BLANKING OUTPUT CONNECTION
•
Pin 4
is the external RGB blanking output, needed to switch the external blanking input (pin 39) of the HIP (TDA9320) into
full-screen blanking mode. This mode is activated when the user selects "RGB" from the possible AV modes. In this
instance, the line is HIGH causing the RGB signals on pins 36 to 38 of I200 to have precedence over the picture.
MSP RESET OUTPUT CONNECTION
•
Pin 5
is the MSP3410D reset line that is low when the MSP is being reset. This line is normally HIGH (+5V) when the TV
is operating correctly. When the TV is in the standby state, this line is low, as there is no +5V signal supply to pull the line
up through resistor R044.
MUTE3 OUTPUT CONNECTION
•
Pin 6
is the Mute3 output needed to mute the ASW amplifier. When this line is HIGH, the internal sub-woofer (optional on
some models) is muted. This occurs if the user has disabled the internal speakers from the speaker configuration menu,
headphones are inserted into the TV, or when the TV is powered off.
DTT DISABLE OUTPUT CONNECTION
•
Pin 7
is the DTT disable output necessary for disconnecting the DTT’s RS232 transmit/receive communication lines from
the microcontroller’s RS232 ports. This output goes to pin 3 of the hex inverter (I004) which is then inverted and fed to
pins 12 & 13 of analogue switch I008. The analogue switch disconnects the RXD and TXD (receive and transmit) lines of
the microcontroller from the DTT’s when pins 12 & 13 of it are LOW.
SHIFT REGISTER CLEAR INPUT (SCLR)
•
Pin 10
is an active low input necessary for clearing the shift register’s data on power-up.
SHIFT REGISTER CLOCK INPUT (SCK)
•
Pin 11
is the shift register clock input necessary for clocking the data into the device. Each bit of data is latched into the
device, on the rising edge of the clock. This clock originates from pin 17 of the microcontroller.
REGISTER CLOCK INPUT (RCK)
•
Pin 12
is the register clock input necessary for latching the data to the output pins. On the rising edge of this pin, all 8
latched bits are transferred to the output pins.
OUTPUT ENABLE INPUT (G)
•
Pin 13
is an active low input necessary for enabling the output ports. This pin is always connected to ground to enable the
outputs.
SHIFT DATA INPUT
•
Pin 14
is the shift data input necessary for transferring the 8 data bits into the device. When this line is HIGH, a logical ‘1’
is latched into the device on the rising edge of SCK. When this line is low during the rising edge of SCK, a logical ‘0’ is
stored instead.
74HC4066 ANALOGUE SWITCH (I007)
INTRODUCTION
The 74HC4066 is a 14-pin high speed CMOS quad bilateral switch. It is used primarily for connecting/disconnecting signals when
out of/in the standby state.
DESCRIPTION
SUPPLY/GROUND CONNECTIONS
•
Pins 14
and
7
are the +5V supply and 0V ground connections respectively. This device is always powered up, even when
then television is in the standby state. Capacitor C025 ensures that the supplies are properly de-coupled.
TXD CONNECTIONS
•
Pin 1
is the RS232 Transmit line from the microcontroller (pin 30) which is routed through to pin 2 of I007 when pin 13 is
HIGH. Under normal operating conditions (and when the TV is NOT in service or diagnose modes), pin 1 is disconnected
from pin 2 (and pin 10 of scart2). When the TV is in service mode, a PC can be connected to scart 2 to perform diagnostic
functions on the chassis (see separate section on diagnostic protocols for more information).
Summary of Contents for C28W40TN
Page 29: ...28 GENERAL BLOCK DIAGRAM ...
Page 91: ...90 CASE DE FONCTIONS EXTRÉMITÉ HAUTE CASE FONCTIONS EXTRÉMITÉ BASSE ...
Page 102: ...101 SCHÉMA SYNOPTIQUE ...
Page 165: ...164 HÖHERE FEATURE BOX NIEDRIGE FEATURE BOX ...
Page 177: ...176 BLOCKSCHALTBILD ...
Page 200: ...199 ...
Page 225: ...224 WAVEFORMS ...
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