Figure 2-1 shows timing waveforms for the address bus and the
RD
and
W
R (
HWR
or
LWR
)
signals during execution of the above instruction with an 8-bit bus, using 3-state access with no
wait states.
Figure 2-1 Address Bus,
RD
, and
WR
(
HWR
or
LWR
) Timing
(8-bit bus, 3-state access, no wait states)
ø
Address bus
RD
WR
(HWR or LWR)
High level
Internal
operation
Fetching
3rd byte
of instruction
Fetching
4th byte
of instruction
Fetching
1st byte of
jump address
Fetching
2nd byte of
jump address
R:W EA
R:W 2nd
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