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Figure 4-6 External Device Access Timing (2) Write Timing
Write cycle
T
1
state
T
2
state
Address
(a) Two-state access
Address bus
AS
WR
(HWR or LWR)
Data bus
ø
Write data
Write cycle
T
1
state
T
2
state
Address
Write data
(b) Three-state access
T
3
state
Address bus
AS
WR
(HWR or LWR)
Data bus
ø
250
