Hitachi H8/300L Series, Programming Manual

Page 1: ...H8 300L Series Programming Manual ...

Page 2: ...the characteristics and performance of Hitachi s semiconductor products Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein 5 No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi Ltd 6 MEDICAL APPLICATIONS Hitachi s products are ...

Page 3: ...ection 2 Instruction Set 31 2 1 Explanation Format 31 ADD add binary byte 31 2 2 Instructions 36 2 2 1 1 ADD add binary byte 36 2 2 1 2 ADD add binary word 37 2 2 2 ADDS add with sign extension 38 2 2 3 ADDX add with extend carry 39 2 2 4 AND AND logical 40 2 2 5 ANDC AND control register 41 2 2 6 BAND bit AND 42 2 2 7 Bcc branch conditionally 44 2 2 8 BCLR bit clear 47 2 2 9 BIAND bit invert AND ...

Page 4: ...word 93 2 2 32 5 MOV move data byte 95 2 2 32 6 MOV move data word 96 2 2 33 MULXU multiply extend as unsigned 98 2 2 34 NEG negate 99 2 2 35 NOP no operation 100 2 2 36 NOT NOT logical complement 101 2 2 37 OR inclusive OR logical 102 2 2 38 ORC inclusive OR control register 103 2 2 39 POP pop data 104 2 2 40 PUSH push data 105 2 2 41 ROTL rotate left 106 2 2 42 ROTR rotate right 107 2 2 43 ROTXL...

Page 5: ...ions 130 2 5 Number of Execution States 138 Section 3 CPU Operation States 145 3 1 Program Execution State 146 3 2 Exception Handling States 146 3 2 1 Types and Priorities of Exception Handling 146 3 2 2 Exception Sources and Vector Table 148 3 2 3 Outline of Exception Handling Operation 148 3 3 Reset State 149 3 4 Power Down State 149 Section 4 Basic Operation Timing 151 4 1 On chip Memory RAM RO...

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Page 7: ...it general registers and a concise optimized instruction set This manual gives detailed descriptions of the H8 300L instructions The descriptions apply to all chips in the H8 300L Series Assembly language programmers should also read the separate H8 300 Series Cross Assembler User s Manual For hardware details refer to the hardware manual of the specific chip ...

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Page 9: ...ions Powerful bit manipulation instructions 8 addressing modes Register direct Rn Register indirect Rn Register indirect with displacement d 16 Rn Register indirect with post increment pre decrement Rn Rn Absolute address aa 8 aa 16 Immediate xx 8 xx 16 Program counter relative d 8 PC Memory indirect aa 8 64 kbyte address space High speed operation All frequently used instructions are executed in ...

Page 10: ...nd DIVXU 16 bits 8 bits instructions operate on word data The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed BCD form Each 4 bit of the byte is treated as a decimal digit Data Structure in General Registers Data of all the sizes above can be stored in general registers as shown in figure 1 1 Data type Register No Data format 1 Bit data RnH Don t care 7 6 5 4 ...

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Page 12: ...6 8 bit general registers R0H R0L R7H R7L which can also be accessed as eight 16 bit registers R0 to R7 There are two control registers the 16 bit program counter PC and the 8 bit condition code register CCR 7 R0H R0L R1L R1H R2L R2H R3L R3H R4L R4H R5L R5H R6L R6H R7L R7H SP 7 0 0 SP Stack Pointer 15 0 PC Program Counter Condition Code Register Carry flag Overflow flag Zero flag Negative flag Hal...

Page 13: ...an be coded as a synonym for R7 As indicated in figure 1 4 R7 SP points to the top of the stack Unused area SP R7 Stack area Figure 1 4 Stack Pointer 1 2 2 Control Registers The CPU has a 16 bit program counter PC and an 8 bit condition code register CCR 1 Program Counter PC This 16 bit register indicates the address of the next instruction the CPU will execute Instructions are fetched by 16 bit w...

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Page 15: ...transfer MOV POP PUSH 1 Arithmetic operations ADD SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU DIVXU CMP NEG 14 Logic operations AND OR XOR NOT 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR 8 Bit manipulation BSET BCLR BNOT BTST BAND BIAND BOR BIOR BXOR BIXOR BLD BILD BST BIST 14 Branch Bcc JMP BSR JSR RTS 5 System control RTE SLEEP LDC STC ANDC ORC XORC NOP 8 Block data transfer EEPMOV 1 Tot...

Page 16: ...ondition code register N N negative bit of CCR Z Z zero bit of CCR V V overflow bit of CCR C C carry bit of CCR PC Program counter SP Stack pointer R7 Imm Immediate data op Operation field disp Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Not 3 8 16 3 bit 8 bit or 16 bit length ...

Page 17: ...Rn aa 16 xx 8 or xx 16 Rn and Rn addressing modes are available for byte or word data The aa 8 addressing mode is available for byte data only The R7 and R7 modes require word operands Do not specify byte size for these two modes POP W SP Rn Pops a 16 bit general register from the stack Equivalent to MOV W SP Rn PUSH W Rn SP Pushes a 16 bit general register onto the stack Equivalent to MOV W Rn SP...

Page 18: ... 1 Rd Rd 2 Rd Adds or subtracts immediate data to or from data in a general register The immediate data must be 1 or 2 DAA DAS B Rd decimal adjust Rd Decimal adjusts adjusts to packed BCD an addition or subtraction result in a general register by referring to the condition code register MULXU B Rd Rs Rd Performs 8 bit 8 bit unsigned multiplication on data in two general registers providing a 16 bi...

Page 19: ...eneral register and another general register or immediate data NOT B Rd Rd Obtains the one s complement logical complement of general register contents Size Operand size B Byte Table 1 5 Shift Instructions Instruction Size Function SHAL SHAR B Rd shift Rd Performs an arithmetic shift operation on general register contents SHLL SHLR B Rd shift Rd Performs a logical shift operation on general regist...

Page 20: ...it No of EAd C ANDs the C flag with the inverse of a specified bit in a general register or memory The bit number is specified by 3 bit immediate data BOR BIOR B B C bit No of EAd C ORs the C flag with a specified bit in a general register or memory C bit No of EAd C ORs the C flag with the inverse of a specified bit in a general register or memory The bit number is specified by 3 bit immediate da...

Page 21: ...rry Clear High or Same C 0 BCS BLO Carry Set Low C 1 BNE Not Equal Z 0 BEQ Equal Z 1 BVC Overflow Clear V 0 BVS Overflow Set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or Equal N V 0 BLT Less Than N V 1 BGT Greater Than Z N V 0 BLE Less or Equal Z N V 1 JMP Branches unconditionally to a specified address BSR Branches to a subroutine at a specified displacement from the current address JSR Branches...

Page 22: ...RC B CCR Imm CCR Logically exclusive ORs the condition code register with immediate data NOP PC 2 PC Only increments the program counter Size Operand size B Byte Table 1 9 Block Data Transfer Instruction Instruction Size Function EEPMOV if R4L 0 then repeat RS R6 R4L 1 R4L until R4L 0 else next Moves a data block according to parameters set in general registers R4L R5 and R6 R4L size of block byte...

Page 23: ...t 0 in port control register 4 PCR4 under the following conditions P47 Input pin Low P46 Input pin High P45 P40 Output pins Low The intended purpose of this BCLR instruction is to switch P40 from output to input Before Execution of BCLR Instruction P47 P46 P45 P44 P43 P42 P41 P40 Input output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low Low PCR4 0 0 ...

Page 24: ...a register PDR4 under the following conditions P47 Input pin Low P46 Input pin High P45 P40 Output pins Low The intended purpose of this BSET instruction is to switch the output level at P40 from Low to High Before Execution of BSET Instruction P47 P46 P45 P44 P43 P42 P41 P40 Input output Input Input Output Output Output Output Output Output Pin state Low High Low Low Low Low Low Low PCR4 0 0 1 1 ...

Page 25: ... P45 to P40 are output pins for these pins the CPU reads the value in PDR4 The CPU therefore reads the value of port 4 as H 40 although the actual value in PDR4 is H 80 Next the CPU sets bit 0 of the read data to 1 changing the value to H 41 Finally the CPU writes this value H 41 back to PDR4 to complete the BSET instruction As a result bit 0 in PDR4 is set to 0 switching pin P40 to High output Ho...

Page 26: ...abs 7 op 8 0 15 15 7 8 7 8 0 0 15 op 7 8 0 Rn Rn Rm or Rm Rn op d 16 Rm Rn or Rn d 16 Rm op Rm Rn or Rn Rm op IMM op Rn xx 8 op IMM xx 16 Rn POP PUSH MOV r r m n r r m n r r m n r r aa 8 Rn or Rn aa 8 n r n r aa 16 Rn or Rn aa 16 n r n r n r Notation op Operation field r r Register field disp Displacement abs Absolute address IMM Immediate data m n Figure 1 5 Instruction Format of Data Transfer In...

Page 27: ...8 0 MULXU DIVXU op m ADDX SUBX Rm DAS NEG NOT ADDS SUBS INC DEC DAA 15 15 op xx 8 ADD ADDX SUBX CMP 7 7 8 8 0 IMM 0 AND OR XOR Rm 15 15 op AND OR XOR xx 8 7 7 8 8 0 0 SHAL SHAR SHLL SHLR op op IMM ROTL ROTR ROTXL ROTXR r n r n r m r n r m r n r n r Notation op Operation field r r Register field IMM Immediate data m n n r n r Figure 1 6 Instruction Format of Arithmetic Logic and Shift Instructions ...

Page 28: ...Rn 7 8 IMM n 0 op 15 op Bit No register direct Rm Operand register indirect Rn 7 8 0 0 0 0 0 0 0 0 0 op 15 op Operand absolute aa 8 Bit No register direct Rm 7 8 abs 0 0 0 0 0 op 15 BAND BOR BXOR BLD BST Operand register direct Rn Bit No immediate xx 3 7 8 IMM 0 op op 15 op 15 op Operand register indirect Rn Bit No immediate xx 3 Operand absolute aa 8 Bit No immediate xx 3 7 8 abs IMM IMM 0 0 0 0 ...

Page 29: ...nd register indirect Rn Bit No immediate xx 3 op 15 op Operand absolute aa 8 Bit No immediate xx 3 7 8 IMM abs 0 0 0 0 0 BIAND BIOR BIXOR BILD BIST r n r Notation op Operation field r r Register field abs Absolute address IMM Immediate data m n Figure 1 7 Instruction Format of Bit Manipulation Instructions Cont ...

Page 30: ... 0 op 15 15 15 7 7 8 op 8 7 8 op 0 disp 0 BSR 0 op disp m abs abs 0 0 0 JMP aa 16 JMP aa 8 0 0 0 0 op JSR Rm 15 15 op op 15 abs 7 7 8 8 0 0 RTS JSR aa 8 abs 7 op 8 0 JSR aa 16 Notation op Operation field cc Condition field r Register field disp Displacement abs Absolute address m r m r Figure 1 8 Instruction Format of Branching Instructions ...

Page 31: ...ng Modes and Effective Address Calculation Table 1 10 lists the eight addressing modes and their assembly language notation Each instruction can use a specific subset of these addressing modes Arithmetic logic and shift instructions use register direct addressing 1 The ADD B ADDX SUBX CMP B AND OR and XOR instructions can also use immediate addressing 6 The MOV instruction uses all the addressing ...

Page 32: ...d 4 which is added to the contents of the specified general register to obtain the operand address For the MOV W instruction the resulting address must be even 4 Register Indirect with Post Increment or Pre Decrement Rn or Rn Register indirect with post increment Rn The Rn mode is used with MOV instructions that load registers from memory It is similar to the register indirect mode but the 16 bit ...

Page 33: ...de is used to generate branch addresses in the Bcc and BSR instructions An 8 bit value in byte 2 of the instruction code is added as a sign extended value to the program counter contents The result must be an even number The possible branching range is 126 to 128 bytes 63 to 64 words from the current address 8 Memory Indirect aa 8 This mode can be used by the JMP and JSR instructions The second by...

Page 34: ...ress Calculation 1 No Addressing mode instruction format Effective address calculation Effective address 1 Register direct Rn None OP reg m reg n reg m 15 8 7 4 3 0 reg n 3 0 3 0 Operand are contained in registers m and n 2 Register indirect Rn OP reg 15 7 6 4 3 0 Operand is at address indicated by register 16 bit register contents 15 0 15 0 ...

Page 35: ...placement 4 Register indirect with pre decrement Rn 16 bit register contents op reg 15 7 6 4 3 0 15 0 15 0 Register is decremented before operand access 1 or 2 Register indirect with post increment Rn 16 bit register contents OP reg 15 7 6 4 3 0 15 0 15 0 Register is incremented after operand access 1 or 2 1 for a byte operand 2 for a word operand 5 Absolute address aa 8 None H FF OP 15 8 7 0 abs ...

Page 36: ...mediate data Immediate xx 16 None OP IMM 15 0 Operand is 2 byte immediate data 7 PC relative d 8 PC PC contents disp OP 15 8 7 0 15 0 15 0 disp Sign extension Destination address 8 Memory indirect aa 8 H 00 OP 15 8 7 0 15 0 abs 16 bit memory contents 15 8 7 0 Destination address 15 0 rag regm regn General register op Operation field disp Displacement abs Absolute address IMM Immediate data ...

Page 37: ...e Condition Code I H N Z V C I Previous value remains unchanged H Set to 1 when there is a carry from bit 3 otherwise cleared to 0 N Set to 1 when the result is negative otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Set to 1 when an overflow occurs otherwise cleared to 0 C Set to 1 when there is a carry from bit 7 otherwise cleared to 0 Description This instruc...

Page 38: ... page Operation The instruction is described in symbolic notation The following symbols are used Symbol Meaning Rd General register destination Rs General register source Rn General register EAd Destination operand EAs Source operand PC Program counter SP Stack pointer CCR Condition code register N N negative flag of CCR Z Z zero flag of CCR V V overflow flag of CCR C C carry flag of CCR disp Disp...

Page 39: ...rect with displacement Rn Rn Register indirect with post increment pre decrement aa 8 aa 16 Absolute address xx 8 xx 16 Immediate d 8 PC Program counter relative aa 8 Memory indirect Operand size Word or byte Byte size is indicated for bit manipulation instructions because these instructions access a full byte in order to read or write one bit Condition code The effect of instruction execution on ...

Page 40: ...rs are 8 bit or 16 bit registers depending on the size of the operand For 8 bit registers the lower three bits of rs rd or rn give the register number The most significant bit is 1 if the lower byte of the register is used or 0 if the upper byte is used Registers are thus indicated as follows 16 Bit register Register rs rd or rn 0 0 0 0 0 1 1 1 1 R0 R1 R7 8 Bit registers rs rd or rn Register 0 0 0...

Page 41: ...arry flag in CCR Bit No 5 C H FF02 BLD 5 H FF02 8 The addressing mode and operand size apply to the register or memory byte containing the bit Number of States Required for Execution The number of states indicated is the number required when the instruction and any memory operands are located in on chip ROM or RAM If ...

Page 42: ...leared to 0 N Set to 1 when the result is negative otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Set to 1 when an overflow occurs otherwise cleared to 0 C Set to 1 when there is a carry from bit 7 otherwise cleared to 0 Description This instruction adds the source operand to the contents of an 8 bit general register and places the result in the general register...

Page 43: ... Z Set to 1 when the result is zero otherwise cleared to 0 V Set to 1 when an overflow occurs otherwise cleared to 0 C Set to 1 when there is a carry from bit 15 otherwise cleared to 0 Description This instruction adds word data in two general registers and places the result in the second general register Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Oper...

Page 44: ...us value remains unchanged C Previous value remains unchanged Description This instruction adds the immediate value 1 or 2 to word data in a general register Unlike the ADD instruction it does not affect the condition code flags Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct ADDS 1 R...

Page 45: ... zero otherwise cleared to 0 V Set to 1 when an overflow occurs otherwise cleared to 0 C Set to 1 when there is a carry from bit 7 otherwise cleared to 0 Description This instruction adds the source operand and carry flag to the contents of an 8 bit general register and places the result in the general register Instruction Formats and Number of Execution States Instruction code Addressing mode Mne...

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Page 47: ... 0 of the immediate data Description This instruction ANDs the condition code register CCR with immediate data and places the result in the condition code register Bits 6 and 4 are ANDed as well as the flag bits No interrupt requests are accepted immediately after this instruction All interrupts including the nonmaskable interrupt NMI are deferred until after the next instruction Instruction Forma...

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Page 49: ...umber of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BAND xx 3 Rd 7 6 0 IMM rd 2 Register indirect BAND xx 3 Rd 7 C 0 rd 0 7 6 0 IMM 0 6 Absolute address BAND xx 3 aa 8 7 E abs 7 6 0 IMM 0 6 Register direct register indirect or absolute addressing ...

Page 50: ...us value remains unchanged C Previous value remains unchanged Description If the specified condition is false this instruction does nothing the next instruction is executed If the specified condition is true a signed displacement is added to the address of the next instruction and execution branches to the resulting address The displacement is a signed 8 bit value which must be even The branch des...

Page 51: ... 0 1 Carry Set Low C 1 X Y Unsigned BNE 0 1 1 0 Not Equal Z 0 X Y Signed or unsigned BEQ 0 1 1 1 Equal Z 1 X Y Signed or unsigned BVC 1 0 0 0 Overflow Clear V 0 BVS 1 0 0 1 Overflow Set V 1 BPL 1 0 1 0 Plus N 0 BMI 1 0 1 1 Minus N 1 BGE 1 1 0 0 Greater or Equal N V 0 X Y Signed BLT 1 1 0 1 Less Than N V 1 X Y Signed BGT 1 1 1 0 Greater Than Z N V 0 X Y Signed BLE 1 1 1 1 Less or Equal Z N V 1 X Y ...

Page 52: ...p 4 PC relative BLS d 8 4 3 disp 4 PC relative BCC BHS d 8 4 4 disp 4 PC relative BCS BLO d 8 4 5 disp 4 PC relative BNE d 8 4 6 disp 4 PC relative BEQ d 8 4 7 disp 4 PC relative BVC d 8 4 8 disp 4 PC relative BVS d 8 4 9 disp 4 PC relative BPL d 8 4 A disp 4 PC relative BMI d 8 4 B disp 4 PC relative BGE d 8 4 C disp 4 PC relative BLT d 8 4 D disp 4 PC relative BGT d 8 4 E disp 4 PC relative BLE ...

Page 53: ...ious value remains unchanged V Previous value remains unchanged C Previous value remains unchanged Description This instruction clears a specified bit in the destination operand to 0 The bit number can be specified by 3 bit immediate data or by the lower three bits of an 8 bit general register The destination operand can be located in a general register or memory The specified bit is not tested be...

Page 54: ...ion code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BCLR xx 3 Rd 7 2 0 IMM rd 2 Register indirect BCLR xx 3 Rd 7 D 0 rd 0 7 2 0 IMM 0 8 Absolute address BCLR xx 3 aa 8 7 F abs 7 2 0 IMM 0 8 Register direct BCLR Rn Rd 6 2 rn rd 2 Register indirect BCLR Rn Rd 7 D 0 rd 0 6 2 rn 0 8 Absolute address BCLR Rn aa 8 7 F abs 6 2 rn 0 8 ...

Page 55: ... value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C ANDed with the inverse of the specified bit Description This instruction ANDs the inverse of a specified bit with the carry flag and places the result in the carry flag The specified bit can be located in a general register or memory The bit number is specified by 3 bit immediate data The operation is ...

Page 56: ... Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BIAND xx 3 Rd 7 6 1 IMM rd 2 Register indirect BIAND xx 3 Rd 7 C 0 rd 0 7 6 1 IMM 0 6 Absolute address BIAND xx 3 aa 8 7 E abs 7 6 1 IMM 0 6 Register direct register indirect or absolute addressing ...

Page 57: ...changed N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Loaded with the inverse of the specified bit Description This instruction loads the inverse of a specified bit into the carry flag The specified bit can be located in a general register or memory The bit number is specified by 3 bit immediate data The operation is shown schematically ...

Page 58: ... Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BILD xx 3 Rd 7 7 1 IMM rd 2 Register indirect BILD xx 3 Rd 7 C 0 rd 0 7 7 1 IMM 0 6 Absolute address BILD xx 3 aa 8 7 E abs 7 7 1 IMM 0 6 Register direct register indirect or absolute addressing ...

Page 59: ...vious value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C ORed with the inverse of the specified bit Description This instruction ORs the inverse of a specified bit with the carry flag and places the result in the carry flag The specified bit can be located in a general register or memory The bit number is specified by 3 bit immediate data The operation ...

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Page 61: ...us value remains unchanged N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged Description This instruction stores the inverse of the carry flag to a specified bit location in a general register or memory The bit number is specified by 3 bit immediate data The operation is shown schematically below ...

Page 62: ...and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BIST xx 3 Rd 6 7 1 IMM rd 2 Register indirect BIST xx 3 Rd 7 D 0 rd 0 6 7 1 IMM 0 8 Absolute address BIST xx 3 aa 8 7 F abs 6 7 1 IMM 0 8 Register direct register indirect or absolute addressing ...

Page 63: ...ue remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Exclusive ORed with the inverse of the specified bit Description This instruction exclusive ORs the inverse of a specified bit with the carry flag and places the result in the carry flag The specified bit can be located in a general register or memory The bit number is specified by 3 bit immediate data The...

Page 64: ... Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BIXOR xx 3 Rd 7 5 1 IMM rd 2 Register indirect BIXOR xx 3 Rd 7 C 0 rd 0 7 5 1 IMM 0 6 Absolute address BIXOR xx 3 aa 8 7 E abs 7 5 1 IMM 0 6 Register direct register indirect or absolute addressing ...

Page 65: ...vious value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Loaded with the specified bit Description This instruction loads a specified bit into the carry flag The specified bit can be located in a general register or memory The bit number is specified by 3 bit immediate data The operation is shown schematically below The value of the specified bit is not...

Page 66: ...umber of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BLD xx 3 Rd 7 7 0 IMM rd 2 Register indirect BLD xx 3 Rd 7 C 0 rd 0 7 7 0 IMM 0 6 Absolute address BLD xx 3 aa 8 7 E abs 7 7 0 IMM 0 6 Register direct register indirect or absolute addressing ...

Page 67: ...s value remains unchanged N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged Description This instruction inverts a specified bit in a general register or memory location The bit number is specified by 3 bit immediate data or by the lower three bits of a general register The operation is shown schematically be...

Page 68: ...rmats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BNOT xx 3 Rd 7 1 0 IMM rd 2 Register indirect BNOT xx 3 Rd 7 D 0 rd 0 7 1 0 IMM 0 8 Absolute address BNOT xx 3 aa 8 7 F abs 7 1 0 IMM 0 8 Register direct BNOT Rn Rd 6 1 rn rd 2 Register indirect BNOT Rn Rd 7 D 0 rd 0 6 1 rn 0 8 Absolute address BNOT R...

Page 69: ...nged N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C ORed with the specified bit Description This instruction ORs a specified bit with the carry flag and places the result in the carry flag The specified bit can be located in a general register or memory The bit number is specified by 3 bit immediate data The operation is shown schematical...

Page 70: ...Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BOR xx 3 Rd 7 4 0 IMM rd 2 Register indirect BOR xx 3 Rd 7 C 0 rd 0 7 4 0 IMM 0 6 Absolute address BOR xx 3 aa 8 7 4 abs 7 4 0 IMM 0 6 Register direct register indirect or absolute addressing ...

Page 71: ...ious value remains unchanged V Previous value remains unchanged C Previous value remains unchanged Description This instruction sets a specified bit in the destination operand to 1 The bit number can be specified by 3 bit immediate data or by the lower three bits of an 8 bit general register The destination operand can be located in a general register or memory The specified bit is not tested befo...

Page 72: ...ion code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BSET xx 3 Rd 7 0 0 IMM rd 2 Register indirect BSET xx 3 Rd 7 D 0 rd 0 7 0 0 IMM 0 8 Absolute address BSET xx 3 aa 8 7 F abs 7 0 0 IMM 0 8 Register direct BSET Rn Rd 6 0 rn rd 2 Register indirect BSET Rn Rd 7 D 0 rd 0 6 0 rn 0 8 Absolute address BSET Rn aa 8 7 F abs 6 0 rn 0 8 ...

Page 73: ...pushes the program counter PC value onto the stack then adds a specified displacement to the program counter value and branches to the resulting address The program counter value used is the address of the instruction following the BSR instruction The displacement is a signed 8 bit value which must be even The possible branching range is 126 to 128 bytes from the address of the BSR instruction Ins...

Page 74: ...ious value remains unchanged N Previous value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged Description This instruction stores the carry flag to a specified flag location in a general register or memory The bit number is specified by 3 bit immediate data The operation is shown schematically below ...

Page 75: ...es Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BST xx 3 Rd 6 7 0 IMM rd 2 Register indirect BST xx 3 Rd 7 D 0 rd 0 6 7 0 IMM 0 8 Absolute address BST xx 3 aa 8 7 F abs 6 7 0 IMM 0 8 Register direct register indirect or absolute addressing ...

Page 76: ...ns unchanged Z Set to 1 when the specified bit is zero otherwise cleared to 0 V Previous value remains unchanged C Previous value remains unchanged Description This instruction tests a specified bit in a general register or memory location and sets or clears the Zero flag accordingly The bit number can be specified by 3 bit immediate data or by the lower three bits of an 8 bit general register The...

Page 77: ...Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BTST xx 3 Rd 7 3 0 IMM rd 2 Register indirect BTST xx 3 Rd 7 C 0 rd 0 7 3 0 IMM 0 6 Absolute address BTST xx 3 aa 8 7 E abs 7 3 0 IMM 0 6 Register direct BTST Rn Rd 6 3 rn rd 2 Register indirect BTST Rn Rd 7 C 0 rd 0 6 3 rn 0 6 Absolute address BTST Rn aa 8 7 E abs 6 3 r...

Page 78: ...evious value remains unchanged Z Previous value remains unchanged V Previous value remains unchanged C Exclusive ORed with the specified bit Description This instruction exclusive ORs a specified bit with the carry flag and places the result in the carry flag The specified bit can be located in a general register or memory The bit number is specified by 3 bit immediate data The operation is shown ...

Page 79: ...umber of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct BXOR xx 3 Rd 7 5 0 IMM rd 2 Register indirect BXOR xx 3 Rd 7 C 0 rd 0 7 5 0 IMM 0 6 Absolute address BXOR xx 3 aa 8 7 E abs 7 5 0 IMM 0 6 Register direct register indirect or absolute addressing ...

Page 80: ...d to 0 V Set to 1 when an overflow occurs otherwise cleared to 0 C Set to 1 when there is a borrow from bit 7 otherwise cleared to 0 Description This instruction subtracts an 8 bit source register or immediate data from an 8 bit destination register and sets the condition code flags according to the result The destination register is not altered Instruction Formats and Number of Execution States I...

Page 81: ...sult is zero otherwise cleared to 0 V Set to 1 when an overflow occurs otherwise cleared to 0 C Set to 1 when there is a borrow from bit 15 otherwise cleared to 0 Description This instruction subtracts a source register from a destination register and sets the condition code flags according to the result The destination register is not altered Instruction Formats and Number of Execution States Ins...

Page 82: ...eared to 0 V Unpredictable C Set to 1 when there is a carry from bit 7 otherwise left unchanged Description When the result of an addition operation performed by the ADD B or ADDX instruction on 4 bit BCD data is contained in an 8 bit general register and the carry and half carry flags the DAA instruction adjusts the result by adding H 00 H 06 H 60 or H 66 to the general register according to the ...

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Page 84: ...tion on 4 bit BCD data is contained in an 8 bit general register and the carry and half carry flags the DAA instruction adjusts the result by adding H 00 H FA H A0 or H 9A to the general register according to the table below Valid results are not assured if this instruction is executed under conditions other than those stated above Status before adjustment C flag Upper nibble H flag Lower nibble V...

Page 85: ...hen the result is zero otherwise cleared to 0 V Set to 1 when an overflow occurs the previous value in Rd was H 80 otherwise cleared to 0 C Previous value remains unchanged Description This instruction decrements an 8 bit general register and places the result in the general register Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte...

Page 86: ... value remains unchanged Description This instruction divides a 16 bit general register by an 8 bit general register and places the result in the 16 bit general register The quotient is placed in the lower byte The remainder is placed in the upper byte The operation is shown schematically below Rd Rs RdH RdL Dividend Divisor Remainder Quotient 16 bits 8 bits 8 bits 8 bits Rd Valid results Kd N Z a...

Page 87: ...sion an overflow will occur if the divisor byte is equal to or less than the upper byte of the dividend For example H FFFF H 01 H FFFF causes an overflow The quotient has more than 8 bits Overflows can be avoided by using a subprogram like the following A work register is required To perform DIVXU R0L R1 MOV B H 00 R2H CMP B R0L R1H BCC L1 DIVXU R0L R1 1 MOV B R1L R2L BRA L2 L1 MOV B R1H R2L 2 DIV...

Page 88: ...82 R0L Divisor R1 Dividend R1 Remainder Quotient 1 R1 Dividend R2 H 00 Dividend High 2 R1 Partial remainder Dividend Low R2 Partial remainder Quotient High 3 R1 Remainder Quotient Low R2 Quotient 4 ...

Page 89: ...k of data from the memory location specified in general register R5 to the memory location specified in general register R6 General register R4L gives the byte length of the block Data are transferred a byte at a time After each byte transfer R5 and R6 are incremented and R4Lis decremented When R4L reaches 0 the transfer ends and the next instruction is executed No interrupt requests are accepted ...

Page 90: ...Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states EEPMOV 7 B 5 C 5 9 8 F 9 4n n is the initial value in R4L 0 n 255 Although n bytes of data are transferred memory is accessed 2 n 1 times requiring 4 n 1 states ...

Page 91: ...hen the result is zero otherwise cleared to 0 V Set to 1 when an overflow occurs the previous value in Rd was H 7F otherwise cleared to 0 C Previous value remains unchanged Description This instruction increments an 8 bit general register and places the result in the general register Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte...

Page 92: ...revious value remains unchanged C Previous value remains unchanged Description This instruction branches unconditionally to a specified destination address The destination address must be even Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register indirect JMP Rn 5 9 0 rn 0 4 Absolute address JMP a...

Page 93: ...anged Description This instruction pushes the program counter onto the stack then branches to a specified destination address The program counter value pushed on the stack is the address of the instruction following the JSR instruction The destination address must be even Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4t...

Page 94: ...m the source operand Description This instruction loads the source operand contents into the condition code register CCR Bits 4 and 6 are loaded as well as the flag bits No interrupt requests are accepted immediately after this instruction All interrupts are deferred until after the next instruction Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1...

Page 95: ...89 2 2 32 1 MOV move data byte Operation Rs Rd Assembly Language Format MOV B Rs Rd Operand Size Byte Condition Code I H N Z V C 0 ...

Page 96: ...o 0 Z Set to 1 when the data value is zero otherwise cleared to 0 V Cleared to 0 C Previous value remains unchanged Description This instruction moves one word of data from a source register to a destination register and sets condition code flags according to the data value Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte ...

Page 97: ...is negative otherwise cleared to 0 Z Set to 1 when the data value is zero otherwise cleared to 0 V Cleared to 0 C Previous value remains unchanged Description This instruction moves one byte of data from a source operand to a destination register and sets condition code flags according to the data value The MOV B R7 Rd instruction should never be used because it leaves an odd value in the stack po...

Page 98: ...e 4th byte No of states Immediate MOV B xx 8 Rd F rd IMM 2 Register indirect MOV B RS Rd 6 8 0 rs rd 4 Register indirect with displacement MOV B d 16 Rs Rd 6 E 0 rs rd disp 6 Register indirect with post increment MOV B Rs Rd 6 C 0 rs rd 6 Absolute address MOV B aa 8 Rd 2 rd abs 4 Absolute address MOV B aa 16 Rd 6 A 0 rd abs 6 ...

Page 99: ...eared to 0 V Cleared to 0 C Previous value remains unchanged Description This instruction moves one word of data from a source operand to a destination register and sets condition code flags according to the data value If the source operand is in memory it must be located at an even address MOV W R7 Rd is identical in machine language to POP W Rd Note that the LSIs in the H8 300L Series contain on...

Page 100: ...d byte 3rd byte 4th byte No of states Immediate MOV W xx 16 Rd 7 9 0 0 rd IMM 4 Register indirect MOV W RS Rd 6 9 0 rs 0 rd 4 Register indirect with displacement MOV W d 16 Rs Rd 6 F 0 rs 0 rd disp 6 Register indirect with post increment MOV W Rs Rd 6 D 0 rs 0 rd 6 Absolute address MOV W aa 16 Rd 6 B 0 0 rd abs 6 ...

Page 101: ...ng to the data value The MOV B Rs R7 instruction should never be used because it leaves an odd value in the stack pointer See section 3 2 3 for details The instruction MOV B RnH Rn or MOV B RnL Rn decrements register Rn then moves the upper or lower byte of the decremented result to memory Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2n...

Page 102: ...vious value remains unchanged Description This instruction moves one word of data from a general register to memory and sets condition code flags according to the data value The destination address in memory must be even MOV W Rs R7 is identical in machine language to PUSH W Rs The instruction MOV W Rn Rn decrements register Rn by 2 then moves the decremented result to memory Note that the LSIs in...

Page 103: ... Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register indirect MOV W Rs Rd 6 9 1 rd 0 rs 4 Register indirect with displacement MOV W Rs d 16 Rd 6 F 1 rd 0 rs disp 6 Register indirect with pre decrement MOV W Rs Rd 6 D 1 rd 0 rs 6 Absolute address MOV W Rs aa 16 6 B 8 0 rs abs 6 ...

Page 104: ...egister and places the result in the destination register The source register is an 8 bit register The destination register is a 1 6 bit register containing the data to be multiplied in the lower byte The upper byte is ignored The result is placed in both bytes of the destination register The operation is shown schematically below Don t care Multiplicand X Multiplier Product Rd Rs Rd 8 bits 8 bits...

Page 105: ...ister was H 80 otherwise cleared to 0 C Set to 1 when there is a borrow from bit 7 the previous contents of the destination register was not H 00 otherwise cleared to 0 Description This instruction replaces the contents of an 8 bit general register with its two s complement subtracts the register contents from H 00 If the original contents of the destination register was H 80 the register value re...

Page 106: ...Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged Description This instruction only increments the program counter causing the next instruction to be executed The internal state of the CPU does not change Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of ...

Page 107: ...e cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Cleared to 0 C Previous value remains unchanged Description This instruction replaces the contents of an 8 bit general register with its one s complement subtracts the register contents from H FF Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th ...

Page 108: ... Z Set to 1 when the result is zero otherwise cleared to 0 V Cleared to 0 C Previous value remains unchanged Description This instruction ORs the source operand with the contents of an 8 bit general register and places the result in the general register Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states...

Page 109: ...te data C ORed with bit 0 of the immediate data Description This instruction ORs the condition code register CCR with immediate data and places the result in the condition code register Bits 6 and 4 are ORed as well as the flag bits No interrupt requests are accepted immediately after this instruction All interrupts are deferred until after the next instruction Instruction Formats and Number of Ex...

Page 110: ... when the data value is zero otherwise cleared to 0 V Cleared to 0 C Previous value remains unchanged Description This instruction pops data from the stack to a 16 bit general register and sets condition code flags according to the data value POP W Rn is identical in machine language to MOV W SP Rn Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1s...

Page 111: ...hen the data value is zero otherwise cleared to 0 V Cleared to 0 C Previous value remains unchanged Description This instruction pushes data from a 16 bit general register onto the stack and sets condition code flags according to the data value PUSH W Rn is identical in machine language to MOV W Rn SP Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands...

Page 112: ...otherwise cleared to 0 V Cleared to 0 C Receives the previous value in bit 7 Description This instruction rotates an 8 bit general register one bit to the left The most significant bit is rotated to the least significant bit and also copied to the carry flag The operation is shown schematically below C Bit 7 Bit 0 MSB LSB Instruction Formats and Number of Execution States Instruction code Addressi...

Page 113: ... otherwise cleared to 0 V Cleared to 0 C Receives the previous value in bit 0 Description This instruction rotates an 8 bit general register one bit to the right The least significant bit is rotated to the most significant bit and also copied to the carry flag The operation is shown schematically below Bit 7 Bit 0 C MSB LSB Instruction Formats and Number of Execution States Instruction code Addres...

Page 114: ...cleared to 0 V Cleared to 0 C Receives the previous value in bit 7 Description This instruction rotates an 8 bit general register one bit to the left through the carry flag The carry flag is rotated into the least significant bit of the register The most significant bit rotates into the carry flag The operation is shown schematically below C Bit 7 Bit 0 MSB LSB Instruction Formats and Number of Ex...

Page 115: ...therwise cleared to 0 V Cleared to 0 C Receives the previous value in bit 0 Description This instruction rotates an 8 bit general register one bit to the right through the carry flag The least significant bit is rotated into the carry flag The carry flag rotates into the most significant bit The operation is shown schematically below Bit 7 Bit 0 C MSB LSB Instruction Formats and Number of Executio...

Page 116: ......

Page 117: ...ous value remains unchanged C Previous value remains unchanged Description This instruction returns from a subroutine It pops the program counter PC from the stack Program execution continues from the address restored to the program counter The PC contents at the time of execution of this instruction are lost Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem ...

Page 118: ...wise cleared to 0 C Receives the previous value in bit 7 Description This instruction shifts an 8 bit general register one bit to the left The most significant bit shifts into the carry flag and the least significant bit is cleared to 0 The operation is shown schematically below C Bit 7 Bit 0 MSB LSB 0 The SHAL instruction is identical to the SHLL instruction except for its effect on the overflow ...

Page 119: ...hen the result is negative otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Cleared to 0 C Receives the previous value in bit 0 Description This instruction shifts an 8 bit general register one bit to the right The most significant bit remains unchanged The sign of the result does not change The least significant bit shifts into the carry flag The operation is sho...

Page 120: ...114 Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct SHAR Rd 1 1 8 rd 2 ...

Page 121: ... cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Cleared to 0 C Receives the previous value in bit 0 Description This instruction shifts an 8 bit general register one bit to the left The least significant bit is cleared to 0 The most significant bit shifts into the carry flag The operation is shown schematically below C Bit 7 Bit 0 MSB LSB 0 The SHLL instruction is identic...

Page 122: ...116 Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct SHLL Rd 1 0 0 rd 2 ...

Page 123: ...ged N Set to 1 when the result is negative otherwise cleared to 0 Z Set to 1 when the result is zero otherwise cleared to 0 V Cleared to 0 C Receives the previous value in bit 0 Description This instruction shifts an 8 bit general register one bit to the right The most significant bit is cleared to 0 The least significant bit shifts into the carry flag The operation is shown schematically below Bi...

Page 124: ...118 Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct SHLR Rd 1 1 0 rd 2 ...

Page 125: ...n mode Its internal state remains unchanged but the CPU stops executing instructions and waits for an exception handling request interrupt or reset When it receives an exception handling request the CPU exits the power down mode and begins the exception handling sequence If the interrupt mask I bit is set to 1 the power down mode can be released only by a nonmaskable interrupt NMI or reset For inf...

Page 126: ...ged Z Previous value remains unchanged V Previous value remains unchanged C Previous value remains unchanged Description This instruction copies the condition code register CCR to a specified general register Bits 6 and 4 are copied as well as the flag bits Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1 st byte 2nd byte 3rd byte 4th byte No of s...

Page 127: ...en an overflow occurs otherwise cleared to 0 C Set to 1 when there is a borrow from bit 7 otherwise cleared to 0 Description This instruction subtracts an 8 bit source register from an 8 bit destination register and places the result in the destination register Only register direct addressing is supported To subtract immediate data it is necessary to use the SUBX B instruction first setting the ze...

Page 128: ...122 Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of states Register direct SUB B Rs Rd 1 8 rs rd 2 ...

Page 129: ...1 when the result is zero otherwise cleared to 0 V Set to 1 when an overflow occurs otherwise cleared to 0 C Set to 1 when there is a borrow from bit 15 otherwise cleared to 0 Description This instruction subtracts a 16 bit source register from a 16 bit destination register and places the result in the destination register Instruction Formats and Number of Execution States Instruction code Address...

Page 130: ...s value remains unchanged C Previous value remains unchanged Description This instruction subtracts the immediate value 1 or 2 from word data in a general register Unlike the SUB instruction it does not affect the condition code flags The SUBS instruction does not permit byte operands Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1 st byte 2nd by...

Page 131: ...he result is zero otherwise cleared to 0 V Set to 1 when an overflow occurs otherwise cleared to 0 C Set to 1 when there is a borrow from bit 7 otherwise cleared to 0 Description This instruction subtracts the source operand and carry flag from the contents of an 8 bit general register and places the result in the general register Instruction Formats and Number of Execution States Instruction code...

Page 132: ...t to 1 when the result is zero otherwise cleared to 0 V Cleared to 0 C Previous value remains unchanged Description This instruction exclusive ORs the source operand with the contents of an 8 bit general register and places the result in the general register Instruction Formats and Number of Execution States Instruction code Addressing mode Mnem Operands 1st byte 2nd byte 3rd byte 4th byte No of s...

Page 133: ... Exclusive ORed with bit 0 of the immediate data Description This instruction exclusive ORs the condition code register CCR with immediate data and places the result in the condition code register Bits 6 and 4 are exclusive ORed as well as the flag bits No interrupt requests are accepted immediately after this instruction All interrupts including the nonmaskable interrupt NMI are deferred until af...

Page 134: ...0L CPU Only the first byte bits 15 to 8 of the first word of the instruction code is indicated here Indicates that the most significant bit of the 2nd byte bit 7 of 1st word of instruction code is 0 Indicates that the most significant bit of the 2nd byte bit 7 of 1st word of instruction code is 1 ...

Page 135: ...BSR BOR BIOR BXOR BIXOR BAND BIAND ANDC AND BNE RTE LDC BEQ NOT NEG BLD BILD BST BIST ADD SUB BVC BVS MOV INC DEC BPL JMP ADDS SUBS BMI EEPMOV MOV CMP BGE BLT ADDX SUBX BGT JSR DAA DAS BLE MOV ADD ADDX CMP SUBX OR XOR AND MOV MOV The PUSH and POP instructions are equivalent in machine language to the MOV instruction See the descriptions of individual instructions in section 2 2 Instructions for de...

Page 136: ...2 0 4 MOV B aa 16 Rd B aa 16 Rd8 4 0 6 MOV B Rs Rd B Rs8 Rd16 2 0 4 MOV B Rs d 16 Rd B Rs8 d 16 Rd16 4 0 6 MOV B Rs Rd B Rd16 1 Rd16 Rs8 Rd16 2 0 6 MOV B Rs aa 8 B Rs8 aa 8 2 0 4 MOV B Rs aa 16 B Rs8 aa 16 4 0 6 MOV W xx 16 Rd W xx 16 RD 4 0 4 MOV W Rs Rd W Rs16 Rd16 2 0 2 MOV W Rs Rd Rs16 Rd16 2 0 4 MOV W d 16 Rs Rd W d 16 Rs16 Rd1 6 4 0 6 MOV W Rs Rd W Rs16 Rd16 Rs16 2 Rs16 2 0 6 MOV W aa 16 Rd ...

Page 137: ... 2 3 2 SUB B Rs Rd B Rd8 Rs8 Rd8 2 2 SUB W Rs Rd W Rd16 Rs16 Rd16 2 1 2 SUBX B xx 8 Rd B Rd8 xx 8 C Rd8 2 2 2 SUBX B Rs Rd B Rd8 Rs8 C Rd8 2 2 2 SUBS W 1 Rd W Rd16 1 Rd16 2 2 SUBS W 2 Rd W Rd16 2 Rd16 2 2 DEC B Rd B Rd8 1 Rd8 2 2 DAS B Rd B Rd8 decimal adjust Rd8 2 2 NEG B Rd B 0 Rd Rd 2 2 CMP B xx 8 Rd B Rd8 xx 8 2 2 CMP B Rs Rd B Rd8 Rs8 2 2 CMP W Rs Rd W Rd16 Rs16 2 1 2 MULXU B Rs Rd B Rd8xRs8 ...

Page 138: ...perand Size Operation xx 8 16 Rn Rn d 16 Rn Rn Rn aa 8 16 d 8 PC aa Implied Condition Code No of States I H N Z V0 C SHAL B Rd B b7 b0 0 C 2 2 SHAR B Rd B C b7 b0 2 0 2 SHLL B Rd B b7 b0 0 C 2 0 2 SHLR B Rd B b7 b0 0 C 2 0 0 2 ROTXL B Rd B C b7 b0 2 0 2 ROTXR B Rd B C b7 b0 2 0 2 ROTL B Rd B C ...

Page 139: ...nic Operand Size Operation xx 8 16 Rn Rn d 16 Rn Rn Rn aa 8 16 d 8 PC aa Implied Condition Code No of States I H N Z V0 C BCLR xx 3 Rd B xx 3 of Rd8 0 2 2 BCLR xx 3 Rd B xx 3 of Rd16 0 4 8 BCLR xx 3 aa 8 B xx 3 of aa 8 0 4 8 BCLR Rn Rd Rd B Rn8 of Rd8 0 2 2 BCLR Rn Rd B Rn8 of Rd 16 0 4 8 ...

Page 140: ...ondition Code No of States I H N Z V0 C BIST xx 3 Rd B xx 3 of Rd8 2 2 BIST xx 3 Rd B xx 3 of Rd16 4 8 BIST xx 3 aa8 B xx 3 of aa 8 4 8 BAND xx 3 Rd B C xx 3 of Rd8 C 2 2 BAND xx 3 Rd B C xx 3 of Rd16 C 4 6 BAND xx 3 aa 8 B C xx 3 of aa 8 C 4 6 BIAND xx 3 Rd B C RI 5G C 2 2 BIAND xx 3 Rd B C RI 5G C 4 6 BIAND xx 3 aa8 B C RI DD C 4 6 BOR xx 3 Rd B Cv xx 3 of Rd8 C 2 2 ...

Page 141: ...I d 8 N 1 2 4 BGE d 8 N V 0 2 4 BLT d 8 N V 1 2 4 BGT d 8 Zv N V 0 2 4 BLE d 8 Zv N V 1 2 4 JMP Rn PC Rn16 2 4 JMP aa 16 PC aa 16 4 6 JMP aa 8 PC aa 8 2 8 BSR SP 2 SP PC SP PC PC d 8 2 6 JSR Rn SP 2 SP PC SP PC Rn16 2 6 JSR aa 16 SP 2 SP PC SP PC aa 16 4 8 JSR aa 8 SP 2 SP PC SP PC aa 8 2 8 RTS PC SP SP 2 SP 2 8 RTE CCR SP SP 2 SP PC SP SP 2 SP 2 10 SLEEP Transit to sleep mode 2 2 LDC xx 8 CCR B x...

Page 142: ... d 16 Rn Rn Rn aa 8 16 d 8 PC aa Implied Condition Code No of States Branching Condition I H N Z V0 C BHI d 8 if condition is true then PC PC d 8 else next CvZ 0 2 4 BLS d 8 CvZ 1 2 4 BCC d 8 BHS d 8 C 0 2 4 BCS d 8 BLO d 8 C 1 2 4 BNE d 8 Z 0 2 4 BEQ d 8 Z 1 2 4 BVC d 8 V 0 2 4 BVS d 8 V 1 2 4 ...

Page 143: ... assumed that the operation code and operand data are in on chip memory For other cases refer to section 2 5 Number of Execution States 1 Set to 1 when there is a carry or borrow at bit 11 otherwise cleared to 0 2 When the result is 0 the previous value remains unchanged otherwise cleared to 0 3 Set to 1 when there is a carry in the adjusted result otherwise the previous value remains unchanged 4 ...

Page 144: ...n chip ROM and an on chip RAM is accessed 1 BSET 0 FF00 From table 2 4 I L 2 J K M N 0 From table 2 3 SI 2 SL 2 Number of states required for execution 2 2 2 2 8 When instruction is fetched from on chip ROM branch address is read from on chip ROM and on chip RAM is used for stack area 2 JSR 30 From table 2 4 I 2 J K 1 L M N 0 From table 2 3 SI SJ SK 2 Number of states required for execution 2 2 1 ...

Page 145: ...W Rs Rd 1 ADDS ADDS W 1 2 Rd 1 ADDX ADDX B xx 8 Rd 1 ADDX B Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd 1 BAND xx 3 Rd 2 1 BAND xx 3 aa 8 2 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8 2 BCC d 8 BHS d 8 2 BCS d 8 BLO d 8 2 BNE d 8 2 BEQ d 8 2 BVC d 8 2 BVS d 8 2 BPL d 8 2 BMI d 8 2 BGE d 8 2 BLT d 8 2 BGT d 8 2 BLE d 8 2 BCLR BCLR xx 3 Rd 1 BCLR xx...

Page 146: ... 1 BILD xx 3 Rd 2 1 BILD xx3 aa 8 2 1 BIOR BIOR xx 3 Rd 1 BIOR xx3 Rd 2 1 BIOR xx 3 aa 8 2 1 BIST BIST xx 3 Rd 1 BIST xx 3 Rd 2 2 BIST xx 3 aa 8 2 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx 3 Rd 2 1 BIXOR xx 3 aa 8 2 1 BLD BLD xx 3 Rd 1 BLD xx 3 Rd 2 2 BLD xx 3 aa 8 2 2 BNOT BNOT xx 3 Rd 1 BNOT XX 3 Rd 2 2 BNOT xx 3 aa 8 2 2 BNOT Rn Rd 1 BNOT Rn Rd 2 2 BNOT Rn aa 8 2 2 BOR BOR xx 3 Rd 1 BOR xx 3 Rd 2 1 BOR ...

Page 147: ...xx 3 aa 8 2 2 BTST BTST xx 3 Rd 1 BTST xx 3 Rd 2 1 BTST xx 3 aa 8 2 1 BTST Rn Rd 1 BTST Rn Rd 2 1 BTST Rn aa 8 2 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 Rd 2 1 BXOR xx 3 aa 8 2 1 CMP CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W Rs Rd 1 DAA DAA B Rd 1 DAS DAS B Rd 1 DEC DEC B Rd 1 DIVXU DIVXU B Rs Rd 1 12 EEPMOV EEPMOV 2 2n 2 1 INC INC B Rd 1 JMP JMP Rn 2 JMP aa 16 2 2 JMP aa 8 2 1 2 JSR JSR Rn 2 1 JSR aa 16 2 1 2 ...

Page 148: ...16 Rd 2 1 MOV B Rs Rd 1 1 MOV B Rs d 16 Rd 2 1 MOV B Rs Rd 1 1 2 MOV B Rs aa 8 1 1 MOV B Rs aa 16 2 1 MOV W xx 16 Rd 2 MOV W Rs Rd 1 MOV W Rs Rd 1 1 MOV W d 16 Rs Rd 2 1 MOV W Rs Rd 1 1 2 MOV W aa 16 Rd 2 1 MOV W Rs Rd 1 1 MOV W Rs d 16 Rd 2 MOV W Rs Rd 1 1 2 MOV W Rs aa 16 2 1 MULXU MULXU B Rs Rd 1 12 NEG NEG B Rd 1 NOP NOP 1 NOT NOT B Rd 1 OR OR B xx 8 Rd 1 OR B Rs Rd 1 ORC ORC xx 8 CCR 1 POP PO...

Page 149: ...TXR B Rd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHLL SHLL B Rd 1 SHAL SHAL B Rd 1 SHAR SHAR B Rd 1 SHLR SHLR B Rd 1 SLEEP SLEEP 1 STC STC CCR Rd 1 SUB SUB B Rs Rd 1 SUB W Rs Rd 1 SUBS SUBS W 1 2 Rd 1 SUBX SUBX B xx 8 Rd 1 SUBX B Rs Rd 1 XOR XOR B xx 8 Rd 1 XOR B Rs Rd 1 XORC XORC xx 8 CCR 1 n Initial value in R4L The source and destination operands are accessed n 1 times each ...

Page 150: ...144 ...

Page 151: ......

Page 152: ... its normal processing flow branching to a start address acquired from a vector table In exception handling caused by an interrupt PC and CCR values are saved to the stack with reference made to a stack pointer R7 3 2 1 Types and Priorities of Exception Handling Exception handling includes processing of reset exceptions and of interrupts Table 3 1 summarizes the factors causing each kind of except...

Page 153: ...eption handling starts as soon as 5 6 pin changes from low to high Low Interrupt End of instruction execution When an interrupt request is made interrupt exception handling starts after execution of the present instruction is completed Interrupt detection is not made upon completion of ANDC ORC XORC and LDC instruction execution nor upon completion of reset exception handling ...

Page 154: ...t high level and reset exception handling is started at the point when the reset conditions are met For details on reset conditions refer to the applicable hardware manual When reset exception handling is started the CPU gets a start address from the exception handling vector table and starts executing the exception handling routine from that address During execution of this routine and immediatel...

Page 155: ...of register contents must always be done in word size and must start from an even numbered address Figure 3 4 Stack State after Completion of Interrupt Exception Handling 3 3 Reset State When the 5 6 pin goes to low level all processing stops and the system goes to reset state The I bit of the condition code register CCR is set masking all interrupts After the 5 6 pin is changed externally from lo...

Page 156: ...150 ...

Page 157: ...manual 4 1 On chip Memory RAM ROM Two state access is employed for high speed access to on chip memory The data bus width is 16 bits allowing access in byte or word size Figure 4 1 shows the on chip memory access cycle φ Internal address bus Internal read signal Internal data bus read access Internal write signal Internal data bus write access Note Bus cycle T1 state T2 state Address Read data Wri...

Page 158: ...in byte size only Access to word data or instruction codes is not possible Figure 4 2 shows the on chip peripheral module access cycle φ Internal address bus Internal read signal Internal data bus read access Internal write signal Internal data bus write access Note An 8 bit data bus is used Bus cycle T1 state T2 state Address Read data Write data a Two state access ...