381
TDRE
TXD
SCK
t
*
X0
X1
X2
X3
X4
X5
X6
X7
Note:
Make sure that t is at least 5 states.
t
*
Y0
Y1
Y2
Y3
Continuous transmission
Figure 11-22 Transmission in Synchronous Mode (Example)
Restrictions when Switching from SCK Pin to Port Function in Synchronous SCI:
1. Problem in Operation
After setting DDR and DR to 1 and using synchronous SCI clock output, when the SCK pin is
switched to the port function at the end of transmission, a low-level signal is output for one half-
cycle before the port output state is established.
When switching to the port function by making the following settings while DDR = 1, DR = 1,
C/
A
= 1, CKE1 = 0, CKE0 = 0, and TE = 1, low-level output occurs for one half-cycle.
(1) End of serial data transmission
(2) TE bit = 0
(3) C/
A
bit = 0 ... switchover to port output
(4) Occurrence of low-level output (see figure 11-23)
SCK/port
Data
TE
C/
A
CKE1
CKE0
Bit 6
Bit 7
(2) TE=0
(3) C/
A
=0
(1) End of transmission
(4) Low-level output
Half-cycle low-level output occurs
Figure 11-23 Operation when Switching from SCK Pin Function to Port Pin Function