491
Table 16-4 and Figure 16-7 show the timing for the external clock output stabilization delay time.
The oscillator and duty correction circuit have the function of regulating the waveform of the
external clock input to the EXTAL pin. When the specified clock signal is input to the EXTAL
pin, internal clock signal output is confirmed after the elapse of the external clock output
stabilization delay time (t
DEXT
). As clock signal output is not confirmed during the t
DEXT
period, the
reset signal should be driven low and the reset state maintained during this time.
Table 16-4 External Clock Output Stabilization Delay Time
Conditions: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.3 V to 5.5 V, V
SS
= AV
SS
= 0 V
Item
Symbol
Min
Max
Unit
Notes
External clock output stabilization
delay time
t
DEXT
*
500
—
µ
s
Figure 16-7
Note:
*
t
DEXT
includes a 10 t
cyc
RES
pulse width (t
RESW
).
V
CC
STBY
EXTAL
ø
RES
t
DEXT
*
Note:
*
t
DEXT
includes a 10 t
cyc
RES
pulse width (t
RESW
).
2.7 V
V
IH
Figure 16-7 External Clock Output Stabilization Delay Time