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73
(2)
(4)
(6)
(5)
(3)
(1)
ø
RES
Internal
address bus
Internal read
signal
Internal write
signal
Internal data bus
(16-bit width)
Vector fetch
Internal
processing
Prefetch of
first program
instruction
(1), (3)
(2), (4)
(5)
(6)
Address of reset vector: (1) = H'000000, (3) = H'000002
Start address (contents of reset vector)
Start address
First instruction of program
Figure 4-2 Reset Sequence (Modes 5 and 7)