65
Address bus
Internal read signal
Internal data bus
Internal write signal
Address
Internal data bus
φ
T state
Bus cycle
1
T state
2
T state
3
Read
access
Write
access
Write data
Read data
Figure 2.17 Access Cycle for On-Chip Supporting Modules
T
, , ,
AS
φ
1
T
2
Address bus
D to D
15
0
RD HWR LWR
High
High impedance
T
3
Address
Figure 2.18 Pin States during Access to On-Chip Supporting Modules
2.9.4
Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit data bus, and whether it is accessed
in two or three states. For details see section 6, Bus Controller.
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