105
Bit 6—Priority Level B6 (IPRB6): Selects the priority level of 8-bit timer channel 2, 3 interrupt
requests.
Bit 6
IPRB6
Description
0
8-bit timer channel 2 and 3 interrupt requests have priority level 0 (low priority)
(Initial value)
1
8-bit timer channel 2 and 3 interrupt requests have priority level 1 (high priority)
Bits 5 and 4—Reserved: This bit can be written and read, but it does not affect interrupt priority.
Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests.
Bit 3
IPRB3
Description
0
SCI0 channel 0 interrupt requests have priority level 0 (low priority)
(Initial value)
1
SCI0 channel 0 interrupt requests have priority level 1 (high priority)
Bit 2—Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests.
Bit 2
IPRB2
Description
0
SCI1 channel 1 interrupt requests have priority level 0 (low priority)
(Initial value)
1
SCI1 channel 1 interrupt requests have priority level 1 (high priority)
Bits 1 and 0—Reserved: This bit can be written and read, but it does not affect interrupt priority.
5.2.3
IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ
0
to IRQ
5
interrupt
requests.
Summary of Contents for H8/3060
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