135
Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the
WAIT
pin.
Bit 0
WAITE
Description
0
WAIT
pin wait input is disabled, and the
WAIT
pin can be used as an
input/output port
(Initial value)
1
WAIT
pin wait input is enabled
6.2.6
Chip Select Control Register (CSCR)
CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals
(
CS
7
to
CS
4
).
If output of a chip select signal
CS
7
to
CS
4
is enabled by a setting in this register, the
corresponding pin functions a chip select signal (
CS
7
to
CS
4
) output regardless of any other
settings. CSCR cannot be modified in single-chip mode.
—
—
—
—
0
Initial value
0
0
0
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Reserved bits
CS7E
CS6E
CS5E
CS4E
Chip select 7 to 4 enable
These bits enable or disable
chip select signal output
Bit
CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of
the corresponding chip select signal.
Bit n
CSnE
Description
0
Output of chip select signal
CSn
is disabled
(Initial value)
1
Output of chip select signal
CSn
is enabled
Note:
n = 7 to 4
Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 1.
Summary of Contents for H8/3060
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Page 748: ...700 H8 3064F ZTAT B mask version Ports 1 2 5 LED 600 Ω Figure 22 8 Sample LED Circuit ...
Page 777: ...729 H8 3062F ZTAT B mask version Ports 1 2 5 LED 600 Ω Figure 22 14 Sample LED Circuit ...
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