335
10.2.9
TPC Output Control Register (TPCR)
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
Bit
Initial value
Read/Write
0
G0CMS0
1
R/W
1
G0CMS1
1
R/W
2
G1CMS0
1
R/W
3
G1CMS1
1
R/W
4
G2CMS0
1
R/W
5
G2CMS1
1
R/W
6
G3CMS0
1
R/W
7
G3CMS1
1
R/W
Group 3 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 3
(TP
15
to TP
12
)
Group 2 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 2
(TP
11
to TP
8
)
Group 1 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 1
(TP
7
to TP
4
)
Group 0 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 0
(TP
3
to TP
0
)
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3 (TP
15
to TP
12
).
Bit 7
G3CMS1
Bit 6
G3CMS0
Description
0
0
TPC output group 3 (TP
15
to TP
12
) is triggered by compare match in 16-bit
timer channel 0
1
TPC output group 3 (TP
15
to TP
12
) is triggered by compare match in 16-bit
timer channel 1
1
0
TPC output group 3 (TP
15
to TP
12
) is triggered by compare match in 16-bit
timer channel 2
1
TPC output group 3 (TP
15
to TP
12
) is triggered by
compare match in 16-bit timer channel 2
(Initial value)
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