632
EXTAL
t
EXr
t
EXf
V
CC
×
0.7
0.3 V
t
EXH
t
EXL
V
CC
×
0.5
Figure 20.6 External Clock Input Timing
V
CC
STBY
EXTAL
φ
(internal or
external)
RES
t
DEXT
V
IH
Figure 20.7 External Clock Output Settling Delay Timing
20.3
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate
φ
.
20.4
Prescalers
The prescalers divide the system clock (
φ
) to generate internal clocks (
φ
/2 to
φ
/4096).
20.5
Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (
φ
). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
Summary of Contents for H8/3060
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Page 748: ...700 H8 3064F ZTAT B mask version Ports 1 2 5 LED 600 Ω Figure 22 8 Sample LED Circuit ...
Page 777: ...729 H8 3062F ZTAT B mask version Ports 1 2 5 LED 600 Ω Figure 22 14 Sample LED Circuit ...
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