Rev. 3.0, 03/01, page 205 of 390
AC97 Transmit Interrupt Enable Register (ATIER) [cont’d]
Bit
Description
Default
3
PCMLFE TX FIFO UNDERRUN Interrupt Enable (PLFETFUNIE):
When this bit is 1, PCMLFE TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, PCMLFE TX FIFO UNDERRUN Interrupt is disabled.
0
2
Line2 TX FIFO UNDERRUN Interrupt Enable (L2TFUNIE):
When this bit is 1, Line 2 TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, Line 2 TX FIFO UNDERRUN Interrupt is disabled.
0
1
HSET TX FIFO UNDERRUN Interrupt Enable (HTTFUNIE):
When this bit is 1, HSET TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, HSET TX FIFO UNDERRUN Interrupt is disabled.
0
0
IO CTRL TX FIFO UNDERRUN Interrupt Enable (IOCTFUNIE):
When this bit is 1, IO CTRL TX FIFO UNDERRUN Interrupt is enabled.
When this bit is 0, IO CTRL TX FIFO UNDERRUN Interrupt is disabled.
0
14.2.19
AC97 TX FIFO Status Register
ATSR, a 32-bit Read Only register, is used to reflect the status of AC97 TX controller. Bits 31-30
are reserved. The other bits are initialized to 0 at reset. ATIER is not initialized in STANDBY
mode.
Bit
31
30
29
28
27
26
25
24
Bit Name
-
-
PLTFRQ PRTFRQ L1TFRQ PCTFRQ PLSTFR
Q
PRSTFR
Q
Initial Value
-
-
0
0
0
0
0
0
R/W
-
-
R
R
R
R
R
R
Bit
23
22
21
20
19
18
17
16
Bit Name
PLFETFR
Q
L2TFRQ HTTFRQ IOCTFRQ PLTFOV PRTFOV L1TFOV PCTFOV
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Bit
15
14
13
12
11
10
9
8
Bit Name
PLSTFO
V
PRSTFO
V
PLFETFO
V
L2TFOV HTTFOV IOCTFOV PLTFUN PRTFUN
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Summary of Contents for HD64465
Page 25: ...Rev 3 0 03 01 page 6 of 390 ...
Page 59: ...Rev 3 0 03 01 page 40 of 390 ...
Page 97: ...Rev 3 0 03 01 page 78 of 390 ...
Page 147: ...Rev 3 0 03 01 page 128 of 390 ...
Page 199: ...Rev 3 0 03 01 page 180 of 390 ...
Page 247: ...Rev 3 0 03 01 page 228 of 390 ...
Page 385: ...Rev 3 0 03 01 page 366 of 390 ...
Page 389: ...Rev 3 0 03 01 page 370 of 390 ...
Page 409: ...Rev 3 0 03 01 page 390 of 390 ...
