3. AUDIO OUTPUT
The MT1379 supports the stereo (2 channel) outputs .
The MT1379 alTrso provides digital output in S/PDIF format. The board supports coaxial S/PDIF input.
AV2300 has also 5.1 channel Class-D amplifier outputs to 8 o hms satelites and 4 ohms
subwoofer.
4 AUDIO DACS
The MT1379 supports several variations of an I
2
S type bus, varying the order of the data bits (leading or no
leading zero bit, left or right alignment within frame, and MSB or LSB first) is possible using the MT1379
internal configuration registers. The I
2
S format uses four stereo data lines and three clock lines. The I
2
S data
and clock lines can be connected directly to one or more audio DAC to generate analog audio output.
The two-channel DAC is an AKM AK4382 . The DACs support up to 192kHz sampling rate.
The outputs of the DACs are differential, not single ended so a buffering circuit is required. The buffer circuits
use National LM833 op-amps to perform the low-pass filtering and the buffering.
5 VIDEO INTERFACE
5.1 Video Display Output
The video output section controls the transfer of video frames stored in memory to the internal TV encoder of the
Vibratto. The output section consists of a programmable CRT controller capable of operating either in Master or
Slave mode.
The video output section features internal line buffers which allow the outgoing luminance and chrominance data
to match the internal clock rates with external pixel clock rates, easily facilitating YUV4: 2:2 to YUV4: 2:0
comp onent and sample conversion. A polyphase filter achieves arbitrary horizontal decimation and interpolation.
Video Bus
The video bus has 8 YUV data pins that transfer luminance and chrominance (YUV) pixels in CCIR601 pixel
format (4:2:2). In this format, there are half as many chrominance (U or V) pixels per line as luminance (Y)
pixels; there are as many chrominance lines as luminance.
Video Post-Processing
The MT1379 video post-processing circuitry provides support for the color conversion, scaling, and filtering
functions through a combination of special hardware and software. Horizontal up-sampling and filtering is done
with a programmable, 7-tap polyphase filter bank for accurate non-integer interpolations. Vertical scaling is
achieved by repeating and dropping lines in accordance with the applicable scaling ratio.
Video Timing
The video bus can be clocked either by double pixel clock and clock qualifier or by a single pixel clock. The
double clock typically is used for TV displays, the single for computer displays.
Summary of Contents for HTD-K180E
Page 4: ...2 SYSTEM BLOCK DIAGRAM and MT1379 PIN DESCRIPTION 2 1 MT1379 PIN DESCRIPTION ...
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Page 13: ...2 1 SYSTEM BLOCK DIAGRAM System block diagram is shown in the following figure ...
Page 21: ...Pay attention the left side Select CD and CD_ROM ISO on the upper left side of screen ...
Page 22: ...Select No Multisession ...
Page 23: ...Format is Mode 1 ...
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Page 25: ...Leave the dates as it is ...
Page 26: ...Leave it as it is ...
Page 27: ...Click the New on the upper right corner of the screen ...
Page 29: ...Click the Burns the current compilation ...
Page 30: ...Then you will see this screen and click the Burn on the right upper side of screen ...
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Page 48: ...THE UPDATED PARTS LIST FOR THIS MODEL IS AVAILABLE ON ESTA ...