3-24
Functional and Operational Characteristics
Hitachi Universal Storage Platform V/VM User and Reference Guide
Mode
Category
Function
Default
MCU/RCU
685
OPEN and
mainframe
Eliminates **Cache Write-Through mode during the
maintenance replacement process for cases where only cache
modules have failed.
The following conditions must be met before setting this mode
to ON, as there is no guard logic:
USP V model only (USP VM does not have more than 2
cache PCBs).
The number of cache PCBs must be four or more.
Therefore, if one PCB is blocked there is still one functional
PCB remaining on the same cache side.
Cache is configured using the "High Performance Cache
Access Model".
Mode 685 = ON (only when more than two cache PCBs exist):
A single cache module failure will cause the entire cache
PCB to be blocked. This causes the cache on that PCB to be
taken out of the cache directory prior to the PCB being
blocked. Therefore when maintenance is started to remove
the blocked cache PCB, no cache isolation or restructuring
needs to take place for that side, so **Cache Write-
Through mode does not occur.
This must be balanced against the reduction in cache size
prior to maintenance being performed. Normally when only
a few modules are failing on a PCB, only those module
groups are blocked reducing cache only by that amount.
With SOM 685=ON even if one module fails, all modules on
the PCB are unavailable as the PCB will be blocked.
Mode 685 = OFF (default):
Failures of a single cache module or multiple modules will
only cause the module groups to become blocked. This will
allow all of the remaining cache on the PCB to remain in
use. But when cache maintenance is started to replace the
blocked modules, the microcode must first reorganize the
cache directory to allow the PCB to be removed. During
this time, which may be many minutes, **Cache Write-
Through mode occurs.
Note that if 75% or more of the cache capacity is failed,
then the entire PCB will be failed by the microcode
regardless of the mode setting.
** Cache Write-Through mode occurs when duplexed write
data cannot be maintained in cache. This forces the
subsystem to write all IO to the parity group before
signaling to the host that the IO has completed.
Note:
This mode must NEVER be set to ON in storage systems
containing only two cache PCBs; otherwise, when a cache
module fails, the only cache PCB on a side will be blocked
causing **Write-Through Mode to occur until maintenance
is performed and the modules are replaced.
Since the failure of a cache module group is treated as the
failure of a cache PCB, the unavailable cache capacity is
the capacity of the entire PCB, instead of just the failed
module group. Therefore the cache capacity may be
reduced by a much larger amount, and the storage system
will run degraded until maintenance can be performed.
OFF MCU/RCU
