Rev. 1.00
26
September 11, 2018
Rev. 1.00
27
September 11, 2018
HT45F4050
A/D NFC Flash MCU
HT45F4050
A/D NFC Flash MCU
Clocking and Pipelining
The main system clock, derived from either a HXT, LXT, HIRC or LIRC oscillator is subdivided
into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented
at the beginning of the T1 clock during which time a new instruction is fetched. The remaining
T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock
cycle forms one instruction cycle. Although the fetching and execution of instructions takes place
in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that
instructions are effectively executed in one instruction cycle. The exception to this are instructions
where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which
case the instruction will take one more instruction cycle to execute.
Fetch Inst. (PC+2)
Execute Inst. (PC+1)
Oscillator Clock
(System Clock)
Phase Clock T1
Phase Clock T2
Phase Clock T3
Phase Clock T4
Program Counter
Pipelining
PC
PC+1
PC+2
Fetch Inst. (PC+1)
Execute Inst. (PC)
Execute Inst. (PC-1)
Fetch Inst. (PC)
System Clocking and Pipelining
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one
cycle to first obtain the actual jump or call address and then another cycle to actually execute the
branch. The requirement for this extra cycle should be taken into account by programmers in timing
sensitive applications.
Execute Inst. 1
Fetch Inst. 2
1
MOV A, [12H]
2
CALL DELAY
3
CPL [12H]
4
:
5
:
6 DELAY:
NOP
Fetch Inst. 1
Execute Inst. 2
Fetch Inst. 3
Flush Pipeline
Fetch Inst. 6
Execute Inst. 6
Fetch Inst. 7
Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the
next instruction to be executed. It is automatically incremented by one each time an instruction
is executed except for instructions, such as "JMP" or "CALL" that demands a jump to a non-
consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low
Register, are directly addressable by the application program.
When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading
the required address into the Program Counter. For conditional skip instructions, once the condition
has been met, the next instruction, which has already been fetched during the present instruction
execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
