Rev. 1.50
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Rev. 1.50
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HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
HT66F0175/HT66F0185
A/D Flash MCU with EEPROM
TMnC0 Register
Bit
7
6
5
4
3
2
1
0
Name
TnP�U
TnCK�
TnCK1
TnCK0
TnON
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
0
0
0
0
0
—
—
—
Bit 7
TnPAU
: TMn Counter Pause control
0: Run
1: Pause
The counter can be paused by setting this bit high. Clearing the bit to zero restores
normal counter operation. When in a Pause condition the TMn will remain powered up
and continue to consume power. The counter will retain its residual value when this bit
changes from low to high and resume counting from this value when the bit changes
to a low value again.
Bit 6~4
TnCK2~TnCK0
: Select TMn Counter clock
000: f
SYS
/4
001: f
SYS
010: f
H
/16
011: f
H
/64
100: f
TBC
101: f
H
110: TCKn rising edge clock
111: TCKn falling edge clock
These three bits are used to select the clock source for the TMn. The external pin clock
source can be chosen to be active on the rising or falling edge. The clock source f
SYS
is
the system clock, while f
H
and f
TBC
are other internal clocks, the details of which can
be found in the oscillator section.
Bit 3
TnON
: TMn Counter On/Off control
0: Off
1: On
This bit controls the overall on/off function of the TMn. Setting the bit high enables
the counter to run while clearing the bit disables the TMn. Clearing this bit to zero
will stop the counter from counting and turn off the TMn which will reduce its power
consumption. When the bit changes state from low to high the internal counter value
will be reset to zero, however when the bit changes from high to low, the internal
counter will retain its residual value until the bit returns high again. If the TMn is in
the Compare Match Output Mode then the TMn output pin will be reset to its initial
condition, as specified by the TnOC bit, when the TnON bit changes from low to high.
Bit 2~0
Unimplemented, read as “0”
