Honeywell bendis king KLN 94 Maintenance Manual Download

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BENDIX/KING

KLN 94

Rev 0, Sept/2000

15599M00.JA

Page 4-27

4.3.3

GPS XPRESS RECEIVER

CAUTION

DO NOT ATTEMPT TO ALIGN OR REPAIR
THE GPS PXPRESS RECEIVER BOARD (P/N
200–08825–0001). THIS BOARD IS NOT A
FIELD SERVICEABLE ASSEMBLY

The GPS Receiver Board, operating in conjunction with the KA 92 antenna provides the Host mi-
croprocessor (on the Main board) with position, velocity, and time information through the RS-232
interface module. The Host microprocessor provides control information to the GPS Receiver
through the RS-232 interface module.

4.3.4

MAIN BOARD

4.3.4.1

General

Refer to

Figures 4-1

(overall block diagram),

4-4

(Host microprocessor diagram),

4-5

(Graphics mi-

croprocessor diagram), and

4-6

(input/output diagram) and applicable sections of the Illustrated

Parts List as an aid for the following discussion.  The Main Board has two microprocessors: the
Host and the Graphics. The Host microprocessor controls all I/O functions of the rear panel con-
nectors as well as the internal communication to the GPS engine and the local NAV Database with
all calculation for flight. It also handles the front panel button and knob interface.  The Graphics
microprocessor controls the Display module and formats all data to the display as well as all inter-
facing to the Compact Flash data card.  The two microporcessors communicate to each other via
a 2 kiloByte Dual Port Static Ram.

4.3.4.2

Main Board Circuitry

4.3.4.2.1

Real Time Clock

The real time clock circuit consists of Y5002 and U5034. It is configured in the battery backup
mode which means it has power applied at all times regardless if the unit is powered on or not.
Communication with the real time clock and the Host microprocessor is accomplished through a
serial peripheral interface consisting of SCLK and a discrete I/O pin of the Host microprocessor.

4.3.4.2.2

Host Microprocessor

The Host microprocessor, U5031, a Motorola MC68HC16Z1, is a high-speed 16 bit microcontrol-
ler which incorporates the following: a 16 bit central processing unit (CPU), system integration
module (SIM), an 8/10-bit analog-to-digital converter (ADC) depicted on

table 4-2

, a queued serial

module (QSM), general purpose timer (GPT), and a 1024-byte standby RAM (SRAM), intercon-
nected by the inter-module bus (IMB). The system clock is software programmed to 20.972MHz.
A 32.768kHz crystal, part of the reference oscillator, is connected across pin 78 and pin 80.

An internal phase-locked loop (PLL) circuit synthesizes the clock signal from the reference oscil-
lator. Design hardware and software configuration supports changes in clock rate during opera-
tion. Because the Host microprocessor is a fully static design, register and memory contents are
not affected by clock rate changes.

4.3.4.2.3

Host Reset Circuit

The Host microprocessor releases the reset line MAIN_HW_RESETn (pin 94 of U5031) only when
the system clock is established and when the external reset line has been released by the external
reset circuit. When locked, the system clock at pin 87 of U5031 should be 8.38MHz immediately
after reset. When powered up, the reset line will only be released when +5V supply is stable.