BENDIX/KING
KLN 94
Rev 0, Sept/2000
15599M00.JA
Page 4-35
The DISCRETE_CS2n signal will be asserted low when the MAIN_DISCRETE_CSn is low, the
MAIN_ADDRESS_BUS1 is high, and the other two MAIN_ADDRESS_BUS signals are low.
4.3.4.2.12.5
Main 2 EPLD Controller
The MAIN2 EPLD controller holds the Display Video decoding, Audio Tone/Clock Generator, and
some discrete line decoding.
4.3.4.2.12.5.1
Creating of Display Video Controller Control Signals.
All the logic for the specific timing requirements for the Video Controller chip in the display assem-
bly is included here. The logic within this function monitors all read and write accesses to the dis-
play assembly. It also decodes the VIDEO_READY from the display assembly, and signals the
Graphics microprocessor when to terminate a write or read cycle by asserting
GRAPHICS_READYn signal line low.
4.3.4.2.12.5.2
Clock Generation.
A divider divides the 32 MHz clock out of the Graphics microprocessor down for the Audio Tone
(1 kHz.) and the PCLK (Approximately 695 kHz.). PCLK is a signal required by the main micro-
processor for OBS sine and cosine read synchronization.
4.3.4.2.12.5.3
Read/Write Separator.
This separator is an exclusive-or function to separate the single line R_Wn from the Main Micro-
processor into individual RDn and WRn signals needed by various chips.
4.3.4.2.12.5.4
Decoding of Discrete Read Chip selects.
The two Discrete Read Chip selects, DISCRETE_CS1_RDn and DISCRETE_CS2_RDn, are as-
serted only when the RDn signal is asserted along with the DISCRETE_CSn signal.
4.3.4.2.12.5.5
Buffer for DBASE_VPP_EN.
The DBASE_VPP_EN is buffered from the DBASE_PROG_MODE signal to enable the Local Da-
tabase Flash VPP line when programming this Flash device.
4.3.4.2.12.5.6
OBS_DRIVE Output.
The OBS DRIVE output is the 450 Hz signal generated by the DUART, but gated by the
OBS_SELECT signal.
4.3.4.2.12.5.7
CompactFlash Presence Logic.
The CF_PRESENT signal is generated from the two Card Detect lines of the Compact Flash Card.
If both CD1n and CD2n are asserted low by having the Compact Flash Card installed the
CF_PRESENT will be asserted high.
4.3.4.2.12.6
Main 3 EPLD Controller
The MAIN3 EPLD controller holds discrete output latches and the adder and latches for the bank
selects.
4.3.4.2.12.6.1
Discrete Output Latches.
Summary of Contents for bendis king KLN 94
Page 2: ...MAINTENANCE MANUAL KLN 94 GPS NAVIGATION SYSTEM ...
Page 11: ...BENDIX KING KLN 94 Rev 0 Sept 2000 15599M00 JWA Page 4 3 FIGURE4 1 KLN 94 UNIT BLOCK DIAGRAM ...
Page 75: ...BENDIX KING KLN 94 Page 5 36 15599M00 JA Rev 0 Sept 2000 THIS PAGE IS RESERVED ...
Page 80: ...BENDIX KING KLN 94 Rev 0 Sept 2000 15599M00 JWA Page 5 45 FIGURE5 3 KTS 143 TEST FIXTURE ...
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