HP 5305 B, Operating And Service Manual

Model 5305B

Theory of Operation

9E-4-12.   Counting Circuits

SECTION IX E

5305B 1300 MHz COUNTER

SUBSECTION IV

THEORY OF OPERATION

9E-4-1     INTRODUCTION.

9E-4-2.    The 5305B consists of two assemblies, Logic

Board A1 and 1300 MHz amplifier A2. Two input chan-

nels for frequency measurements are provided, Channel A

accepts signals from 90 MHz to 1300 MHz and Channel B

is used for signal inputs up to 100 MHz. Channel B signals

are connected directly to the A1  Logic Board. Channel A

signal inputs are routed to the 1300 MHz Amplifier A2.

The following theory describes the two assemblies.

9E-4-3.      A1  LOGIC BOARD

9E-4-4.    A1 consists of the following major circuits;

High-Impedance Amplifier, Counting, Frequency

Multiplier, and 1300 MHz.   Paragraphs 9E-4-5 through

9E-4-30 describe the theory of operation for these circuits.

9E-4-3       High Impedance Amplifier

9E-4-6.

The high-impedance amplifier consists of

three main stages: (1) An input buffer (Q1, Q2) that

provides high input impedance at unity gain. (2) An AGC

(automatic gain control) amplifier (U6B and C) to generate

the required gain to maintain a relatively constant output

with a wide range of inputs. This assures that the counter

will read the proper frequency in the presence of noisy

input signals. (3) A Schmitttrigger U6A and driver U16 to

convert noisy, slowchanging signals to "clean" square

waves with fast rise times to drive the counting circuits.

9E-4-7.    INPUT CIRCUIT OPERATION. The signal

enters the amplifier through dc blocking capacitor C4,

which, along with C7, R10, R7, CR4, and CR2, protects

against large ac peaks at low frequencies. At high

frequencies, R7 and CR4 and CR2 provide the input

protection for the unity-gain boot-strapped sourcefollower

circuit Q1 and Q2.

9E-4-8.     AGC OPERATION. For small signal levels

(below 

≈

10 mV rms), the output of U8 pin 1 is <.6V (with

no input signal, the voltage is about -3.5V). This causes

Q5 and Q4 to turn off which results in Q3 turning on.

The low source-to-drain impedance (50

Ω

)    shunts resistor

R12. The signal passes unattenuated through Q3 to amplifier

U6C. The output at U6B(6) feeds the signal through R33 and

C25. The signal is converted to dc by CR9, C24 and R35. As

the input signal level increases, the AGC voltage at U8(1)

increases above .6 volts to a maximum of 

≈

 +2 volts. Both

CR5 and CR7 begin to conduct and their resistance drops

rapidly to a few ohms, shunting most of the signal to ground.

At the same time, Q5 begins to conduct and causes Q4 to

conduct.

9E-4-9.    When Q4 is full on, it generates more than -5 volts

gate-to-source voltage on Q3. This tends to "pinch off" Q3,

thereby raising its resistance. With R6  as the main signal

path, only a small portion (10 to 20 mV p-p) of a large input

signal (10V p-p) drives amplifier U6C. This prevents

saturation of U6, and prevents the degradation in signal-to-

noise ratio that saturation would cause. Thus Schmitt trigger

U6A is triggered only by the largest signal at the input and

not noise.

9E-4-10.    DC FEEDBACK AND DUTY CYCLE CON-

TROL. The first two amplifier stages of U6 have a fixed

voltage gain of typically 30 to 40 with a bandwidth of 100

MHz. U8 monitors the output of U6B and regulates the dc

level at about 1.3V, regardless of temperature and device

differences.

9E-4-11.   SCHMITT TRIGGER AND OUTPUT.   The

third stage of U6 is used as a Schmitt trigger.This circuit

shapes the .6V p-p sine wave at its input into a .8V p-p

square wave. It will respond to signals less  than 0.3V p-p in

amplitude and thus rejects noise on  the input signal. U16

amplifies the square wave and converts it to TTL levels to

drive U22.

9E-4-13.  The following paragraphs describe the counting

circuits that are common to all input modes. The RANGE

switch enables one of four NOR gates to pass its respective

signal to the Main Gate U13A and to the arm flip-flop,

U17B. The signals are (1) Channel A divided by 16, U12C;

(2) Channel B, U12A; (3) Channel B times 1000(PLO),

U12B; and (4) 10   MHz clock (check), U13B.

9E-4-1