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Figure 4-5 is a block diagram of the power mesh. These circuits convert the ac input power to approximately 300Vdc, and
convert this dc voltage to the proper dc output voltage.
AC Turn-On Circuits
Primary power comes to the input rectifier through a resistor which limits turn-on inrush current to the input filter. Jumper
A1W5 connects the input rectifier and filter as a voltage doubler for 100/120Vac power lines. This jumper is not used for
220/240Vac; thus the input filter develops a dc bus voltage of about 300Vdc for either 100/120 or 220/240Vac power line
voltages. Primary power also comes through line-voltage select switches to the bias power supplies, which provide the
internal operating voltage for the power supply. The line-voltage select switches connect the primary winds of the
bias-supplies transformer for operation at 100, 120, 220, or 240Vac.
The unit checks that the + 5Vdc bias voltage and the ac power line voltage are within acceptable limits as part of its turn-on
sequence. When + 5Vdc comes up, the bias voltage detector resets the overvoltage protection circuit, enables the on-pulse
driver for the PFET switches, and with the ac-surge-&-dropout detector starts the 1-second-delay circuit. After one second,
relay A1K1 bypasses the inrush current-limiting resistor. After 0.1 seconds more, the 1-Second-Delay circuit enables the
PWM through the
DROPOUT signal. The power supply can then provide output power.
When the ac-surge-&-dropout detector detects high or low line voltage, the unit shuts down until an acceptable power-line
voltage returns. Then it repeats the above turn-on sequence. This protects the unit from damage from power-line surges and
brownouts.
DC-to-DC Converter
PFET switches A4Q3 and A4Q4 control current flow from the Input Filter through power transformer T1. The PWM
creates on- and off-pulses for the PFETs. A train of on pulses comes through diodes A4CR4 and A4CR3 to the PFETs’ gates
to turn on the PFETs. The PFETs’ input capacitances hold the PFETs on between on pulses. Off pulses turn on transistors
A4Q1 and A4Q2 which then short the PFETs’ input capacitances and turn off the PFETs.
The on-pulse one-short A2U15B and off-pulse one-shot A2U15A generate the on and off pulses. A2U15A produces a train
of 160 KHz on pulses during the PWM output pulse. Off pulse one-short A2U15A triggers an off pulse at each trailing edge
of the PWM output pulses. Figure 4-5 shows the timing. Driver circuits increase the current drive capability before applying
the pulses to pulse transformers A4T1 and A4T2.
When the PFETs turn on, current flows through the primary of power transformer AlT1 and primary-current monitor
transformer A4T3. The output rectifier A4CR7 is reverse biased and blocks current flow in the AlT1 secondary.
Consequently, the AlT1 transformer stores energy. When the PFETs apply the dc bus voltage to the primary, the primary
current ramps up, storing more and more energy. The A4T3 transformer senses the AlT1 primary current, and the secondary
of A4T3 develops the Ip-RAMP VOLTAGE across resistor A2R108. This linearity increasing voltage predicts the
correction in the supply’s output voltage or current which will occur when the PFETs are turned off. Comparators
monitoring the Ip-RAMP VOLTAGE signal the PWM to turn off the PFETs when Ip-RAMP VOLTAGE exceeds either the
CP CONTROL-PORT voltage or the POWER-LIMIT reference voltage.
When the PFETs turn off, the collapsing magnetic field reverses the polarity of the voltages across the AlT1 primary and
secondary, and current flows from the A1T2 secondary through output rectifier A4CR7 to charge output capacitor A1C8,
A1C9 and A1C10. When the PFETs turn off, the leakage inductance of T1 forces the current to continue to flow in the
primary. Flyback Diodes A4CR13 and A4CR14 protect the PFETs from excess reverse voltage by conducting this current
around the PFETs and back to the input filter.
Summary of Contents for 6038A
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Page 34: ...34 Figure 3 1 Troubleshooting Isolation ...
Page 35: ...35 Figure 3 1 Troubleshooting Isolation continued ...
Page 37: ...37 Figure 3 3 Clock and Primary SA Waveforms ...
Page 40: ...40 Figure 3 4 Readback and Secondary SA Waveforms ...
Page 56: ...56 Figure 3 7 Waveforms ...
Page 62: ...62 Figure 4 1 HP IB Block Diagram ...
Page 65: ...65 Figure 4 2 Front Panel Block Diagram ...
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Page 93: ...93 Figure 6 1 Top View Top Covers Removed ...
Page 94: ...94 Figure 6 2 Main Board A1 Component Location ...
Page 95: ...95 Figure 6 3 Control Board A2 Component Location ...
Page 96: ...96 Figure 6 4 Front Panel Board A3 Component Location ...
Page 97: ...97 Figure 6 5 Power Mesh Board A4 Component Location ...
Page 98: ...98 Figure 6 6 HP IB Board A8 Component Location ...
Page 105: ...105 Figure 3 1 Troubleshooting Isolation option 001 ...
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