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Constant-Current (CC) Circuit
The constant-current circuit compares the output current user-set CC PROGRAM VOLTAGE to produce CC CONTROL
VOLTAGE. As with the CV Circuit, two comparison amplifier loops accomplish the comparison. OCS is the voltage across
current-monitoring resistors A1R27 and A1R28, and it senses the output current for the outerloop. To compensate for the
fraction of the output current which flows through the unit’s output-voltage sensing resistors, CC monitor amplifier A2U1
adds a fraction of VMON to OCS. It amplifies both to produce the outerloop current-sense voltage, I-MON.
I-MON also connects through protective circuitry to rear-panel terminal IM for remote monitoring of the output current. As
output varies from zero to full scale, I-MON varies from 0 to + 5 volts.
Differentiation of IVS develops a current proportional voltage which senses the interloop current flowing into the capacitive
output filter. CC error amplifier A2U2B sums this differentiated innerloop voltage with I-MON and compares the sum to the
CC PROGRAM VOLTAGE to produce CC CONTROL VOLTAGE. In CC mode the CC CONTROL VOLTAGE varies
between about -0.5 Vdc and about +1.0Vdc at the cathode of diode A2CR19. CC clamp A2U2A limits CC PROGRAM
VOLTAGE to about 5.6 peak volts.
Settings of the rear-panel CC programming switches--the B3, B2 and B1 MODE switch settings--allow the CC PROGRAM
VOLTAGE to come from the HP-IB board, from an external voltage applied between terminals IP and P, or from an
external resistor between IP and P. When using an external resistor, current from the CC constant-current source flows
through the resistance to develop CC PROGRAM VOLTAGE.
Overvoltage Protection (OVP) Circuit
The OVP circuit monitors the power supply output voltage and compares it to a preset limit determined by a front-panel
OVP ADJUST potentiometer. If the output voltage exceeds the limit, the OVP Circuit initiates a PWM OFF pulse, which
also triggers the Down Programmer. The OVP Circuit latches itself until it receives OV CLEAR or ac power is turned off.
The bias voltage detector resets the OVP at turn-on of the unit.
Power-Limit Comparator
Two comparisons with Ip-RAMP VOLTAGE provide POWER LIMIT and CONTROL V LIMIT, two of the four inputs for
the PWM. Power Limit is the output of the Power Limit Comparator A2U14A. The comparator compares Ip-RAMP
VOLTAGE with the power-limit reference voltage of about 1.0Vdc. The reference is adjustable with the POWER LIMIT
calibration trim pot A2R25. POWER LIMIT sets the maximum primary current in power transformer AlT1 by going low
and turning off the PWM when Ip-RAMP VOLTAGE exceeds the reference.
Primary current is approximately proportional to output power, and POWER LIMIT turns off the PWM when the
CONTROL V LIMIT would otherwise allow the unit to deliver more than about 200 watts. This occurs during transient
load increases, step increases in CV PROGRAM VOLTAGE and when the combination of the CV PROGRAM VOLTAGE
and the CC PROGRAM VOLTAGE calls for more than 200 watts. The power-limit comparator produces the power-limited
portion of the unit’s output characteristic curve in Figure 4-3 and is the essence of the unit’s autoranging characteristic.
Control-Voltage Comparator
The control-voltage comparator A2U16 produces the CONTROL V LIMIT input to the PWM by comparing Ip-RAMP
VOLTAGE to CP CONTROL-VOLTAGE. In CV or CC operation CP is one diode-drop more than the lower of the CV and
CC CONTROL VOLTAGE. CONTROL V LIMIT goes low and turns off the PWM when Ip-RAMP VOLTAGE exceeds
CP. The A2R113-A2R114 voltage divider steers control of CP by its connection at the anodes of series diodes A2CR19 and
A2CR24. The A2R113-A2R114 voltage divider sets the maximum CP voltage to + 1.5Vdc. As an illustration of CV-CC
selection, suppose the unit is in CV operation and diode A2CR24 is forward biased by a low CV CONTROL VOLTAGE:
Summary of Contents for 6038A
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Page 34: ...34 Figure 3 1 Troubleshooting Isolation ...
Page 35: ...35 Figure 3 1 Troubleshooting Isolation continued ...
Page 37: ...37 Figure 3 3 Clock and Primary SA Waveforms ...
Page 40: ...40 Figure 3 4 Readback and Secondary SA Waveforms ...
Page 56: ...56 Figure 3 7 Waveforms ...
Page 62: ...62 Figure 4 1 HP IB Block Diagram ...
Page 65: ...65 Figure 4 2 Front Panel Block Diagram ...
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Page 93: ...93 Figure 6 1 Top View Top Covers Removed ...
Page 94: ...94 Figure 6 2 Main Board A1 Component Location ...
Page 95: ...95 Figure 6 3 Control Board A2 Component Location ...
Page 96: ...96 Figure 6 4 Front Panel Board A3 Component Location ...
Page 97: ...97 Figure 6 5 Power Mesh Board A4 Component Location ...
Page 98: ...98 Figure 6 6 HP IB Board A8 Component Location ...
Page 105: ...105 Figure 3 1 Troubleshooting Isolation option 001 ...
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