HP 6038A Service Manual Download

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then CV sets CP to less than + 1.5Vdc. CV keeps diodes A2CR19 reverse biased and prevents CC control until the CC
CONTROL VOLTAGE is even lower.

The lower of the control voltages varies between about - 0.5Vdc and + 1.0Vdc regulating the unit’s output. The higher
control voltage has no effect on the output and increases in response to the error voltage in its circuit. When higher, the CC
CONTROL VOLTAGE limits at about 6Vdc. When higher, the CV CONTROL VOLTAGE increases only slightly. In CV
or CC mode CP remains one diode drop more than the lower control voltage and varies from about 0.0 to + 1.5Vdc. In
UNREGULATED mode CP is + 1.0Vdc.

Initial-Ramp Circuit

The control voltage and ramp voltage waveforms in Figure 4-4 show that there is a time delay between when the control
voltage is exceeded and when the PFETS turn off. This cumulative circuit delay causes the PFETS to deliver power even
when no power is requested by the control circuits. To eliminate the delay, the initial-ramp circuit adds a ramp voltage to
Ip-RAM VOLTAGE at the input to the control voltage comparator. The added ramp voltage starts with the 20KHz clock
pulse and causes the combined-ramp voltage to exceed the control voltage earlier, thereby essentially eliminated the PFET
turn-off delay. A two-state RC integrating network consisting of resistors A2R116 and A2R117 and capacitors A2C59 and
A2C61 creates the initial ramp by shaping the 20KHz clock pulses.

Pulse-Width Modulator (PWM)

The PWM generates 20 KHz repetition-rate pulses which vary in length according to the unit’s output requirements. The
pulses start 1.5

s after each 20KHz clock pulse and turn off when any of these four inputs go low: The output of the

control-voltage comparator (CONTROL V LIMIT ), the output of the power-limit comparator (POWER LIMIT), the 20
KHz clock pulse (50% duty cycle limit), or the output of the inhibit gate A2U19A (MASTER ENABLE). As discussed on
Page 68, the PFETs turn on during and turn off at the trailing edges, respectively, of PWM output pulses.

The PWM generates pulses as follows: a 20KHz dock pulse holds the 1.5

s-delay flip-flop A2U13B reset; 1.5

s after the

trailing edge of the 20KHz pulse, the next pulse from the 320 KHz clock oscillator clocks the output of A2U13B high, and
this initiates the PWM pulse from PWM flip-flop A2U13A. When one of the above four inputs to AND-gate A2U19B goes
low, A2U19B resets A2U13A, and the PWM pulse turns off.

Bias Voltage Detector

The bias voltage detector prevents spurious operation, which might occur at turn-on, of the unit if circuits tried to operate
before the + 5Vdc bias voltage is at the clock, PWM, and logic circuits. After turn-on, as the output of the + 5Vdc bias
supply rises from 0Vdc through 1Vdc, three transistor switches in the Bias Voltage Detector turn on. They inhibit the Relay
Driver and the On-Pulse Driver, and they create the power clear signal,

PCLR2 . The transistors inhibit the circuits and hold

PCLR2 low until the unregulated input to the + 5Vdc bias supply is greater than about 11Vdc, an input voltage sufficient to

5Vdc bias output. PCLR2 resets the OVP at turn-on.

AC-Surge-&-Dropout Detector

The ac-surge-&-dropout detector protects the unit from damage from power line voltage surges and dropouts by shutting
down the unit when there is either a 40% overvoltage or a 20ms voltage interruption in the ac power line voltage. The
detector shuts down the unit by inhibiting the PWM through the DROPOUT signal from the 1-Second Delay circuit. Line
Detect signal, which is fullwave-rectified ac from the + 5Vdc secondary of the bias-supplies transformer, senses the power
line voltage.

The dropout detector, including comparators A2U20A and A2U20D, operates by enabling a capacitor timing ramp when
UNE DETECT ceases. Comparator A2U20C monitors the amplitude of UNE DETECT to provide highline voltage
detection.