Control Processor
States
Figure D-7 shows the relationships between the control processor’s states.
Reset
Self-Test
Ready for
Command
Armed
Scanning
Abort
Abort
set
Abort
clear
Abort
set
Abort
set
scan
complete
ARM
command
trigger
event
Passed
and Ready
Running*
Asserted
Running*
Asserted
Reset and Abort are bits written to the
VXI Control Register (Base + 04
16
).
Passed and Ready are bits read from the
VXI Status Register (Base + 04
16
).
Running* is a bit read from the Scan Status
Register (Base + 10
16
).
ARM is a Register-Based command sent to the
Command and Parameter Registers (Base + 08
16
through 0E
16
).
Figure D-7. Control Processor State Diagram
Appendix D
Register-Based Programming 381
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