120
6 Tests and Error Messages
Order in Which POST Tests Are Performed
28h
1-3-3-1
Autosize DRAM
29h
Initialize POST Memory Manager
2Ah
Clear 512 KB base RAM
2Ch
1-3-4-1
RAM failure on address line
1
2Eh
1-3-4-3
RAM failure on data bits
xxxx
1
of low byte of memory bus
2Fh
Enable cache before system BIOS shadow
30h
1-4-1-1
RAM failure on data bits
xxxx
1
of high byte of memory bus
32h
Test CPU bus-clock frequency
33h
Initialize POST Dispatch Manager
36h
Warm start shut down
38h
Shadow system BIOS ROM
3Ah
Autosize cache
3Ch
Advanced configuration of chipset registers
3Dh
Load alternate registers with CMOS values
42h
Initialize interrupt vectors
45h
POST device initialization
46h
2-1-2-3
Check ROM copyright notice
48h
Check video configuration against CMOS
49h
Initialize PCI bus and devices
4Ah
Initialize all video adapters in system
4Bh
Display QuietBoot screen (optional)
4Ch
Shadow video BIOS ROM
4Eh
Display BIOS copyright notice
50h
Display CPU type and speed
51h
Initialize EISA board
Checkpoint
Code
Beeps
POST Routine Description