Hardware Description
H20RN
-
2000.V2 Series Platforms
2 Architecture and Introduction
Version 1.3(Oct.2019)
Beijing Huahuan Electronics Co., Ltd.
11
Table 2-7
Definition of H20RN
-
2000.V2 series platforms external clock
input\output ports
Pin
Definition
Description
1
IN+
IN is Rx
OUT is Tx
2
IN-
3
CGND
4
OUT+
5
OUT-
6
CGND
7
-
8
-
External Time Synchronization Port
On the H20RN
-
2000.V2 series platforms, MX01/PXM01 card provides one 1PPS TOD port, with
configurable input and output, labeled “1PPS TOD”. It uses RJ45 connector as shown in Figure
5, pin definition is shown in Table 2
Table 2-8
External time synchronization port definition of H20RN
-
2000.V2
series platforms
Pin
Definition
Description
1
-
-
2
-
-
3
RS-422_1_N
1PPS -
4
GND
GND
5
GND
GND
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