5-6
IEN HARDWARE REFERENCE
940043-002
IEN 3000 C
ONFIGURATION
This section describes the configuration procedures for the IEN 3000 chassis. Defining the
IEN 3000 chassis to IENView is similar to defining an IEN 1000, IEN 2000, IEN 4000 or
IEN 5000 chassis in that, each port is represented by a unique bus address.
Bus Clock Settings
The standard bus clock is generated within the IEN 3000 chassis backplane. Therefore,
when bus expanding IEN 3000 chassis, it is necessary to adhere to the following bus setting.
Figure 5-3 illustrates the bus clock settings for the IEN 3000 chassis.
Figure 5-3 IEN 3000 Bus Clock Settings
Note:
The standard bus speed must be set to A (factory default) when using a standard bus
extension. If 32 Bit port processors are in use (CID61, LET61, LTR61 or CID63), the use of
Token Ring or Ethernet bus extension is recommended to optimize performance.
0
STANDARD
SW2
KBPS
8
9
A
B
C
D
E
F
4915.2
2457.6
1228.8
0614.4
0307.2
0153.6
0076.8
0038.4
Summary of Contents for IEN 1000
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