This Data Sheet may be revised by subsequent versions ©2004 Eon Silicon Solution, Inc., www.eonssi.com
or modifications due to changes in technical specifications.
25
EN25F16
Rev. F, Issue Date: 2009/03/16
Table 11.100MHz AC Characteristics
(T
a
= - 40°C to 85°C; V
CC
= 2.7-3.6V)
Symbol
Alt Parameter
Min
Typ Max
Unit
F
R
f
C
Serial Clock Frequency for:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, WRSR
D.C.
100
MHz
f
R
Serial Clock Frequency for READ, RDSR, RDID
D.C.
66 MHz
t
CH
1
Serial Clock High Time
4
ns
t
CL
1
Serial Clock Low Time
4
ns
t
CLCH
2
Serial Clock Rise Time (Slew Rate)
0.1
V / ns
t
CHCL
2
Serial Clock Fall Time (Slew Rate)
0.1
V / ns
t
SLCH
t
CSS
CS# Active Setup Time
5
ns
t
CHSH
CS# Active Hold Time
5
ns
t
SHCH
CS# Not Active Setup Time
5
ns
t
CHSL
CS# Not Active Hold Time
5
ns
t
SHSL
t
CSH
CS# High Time
100
ns
t
SHQZ
2
t
DIS
Output Disable Time
6 ns
t
CLQX
t
HO
Output Hold Time
0
ns
t
DVCH
t
DSU
Data In Setup Time
2
ns
t
CHDX
t
DH
Data In Hold Time
5
ns
t
HLCH
HOLD# Low Setup Time ( relative to CLK )
5
ns
t
HHCH
HOLD# High Setup Time ( relative to CLK )
5
ns
t
CHHH
HOLD# Low Hold Time ( relative to CLK )
5
ns
t
CHHL
HOLD# High Hold Time ( relative to CLK )
5
ns
t
HLQZ
2
t
HZ
HOLD# Low to High-Z Output
6 ns
t
HHQX
2
t
LZ
HOLD# High to Low-Z Output
6
ns
t
CLQV
t
V
Output Valid from CLK
8 ns
t
WHSL
3
Write Protect Setup Time before CS# Low
20
ns
t
SHWL
3
Write Protect Hold Time after CS# High
100
ns
t
DP
2
CS# High to Deep Power-down Mode
3 µs
t
RES1
2
CS# High to Standby Mode without Electronic
Signature read
3 µs
t
RES2
2
CS# High to Standby Mode with Electronic
Signature read
1.8 µs
t
W
Write Status Register Cycle Time
10 15 ms
t
PP
Page Programming Time
1.3 5 ms
t
SE
Sector Erase Time
0.09 0.3 s
t
BE
Block Erase Time
0.4 2 s
t
CE
Chip
Erase Time
7 35 s
Note:
1.
t
CH
+
t
CL
must be greater than or equal to 1/
f
C
2. Value guaranteed by characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write status Register instruction when Status Register Protect Bit is set at 1.
