17
Plasma TV Service Manual
14/03/2005
12.15.2. Features
20 to 85 MHz shift clock support
Best
in
Class Set & Hold Times on TxINPUTs
Tx power consumption <130 mW (typ) @85MHz Grayscale
Tx Power-down mode <200µW (max)
Supports VGA, SVGA, XGA and Dual Pixel SXGA.
Narrow bus reduces cable size and cost
Up to 2.38 Gbps throughput
Up to 297.5 Megabytes/sec bandwidth
345 mV (typ) swing LVDS devices for low EMI
PLL requires no external components
Compatible with TIA/EIA-644 LVDS standard
Low profile 56-lead or 48-lead TSSOP package
DS90C385 also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package
12.15.3. Pin Description
DS90C385 MTD56 (TSSOP) Package Pin Description-FPD Link Transmitter
Pin Name
I/O
No.
Description
TxIN
I
28
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines
FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+
O
4
Positive LVDS differentiaI data output.
TxOUT-
O
4
Negative LVDS differential data output.
TxCLKIN
I
1
TTL Ievel clock input. Pin name TxCLK IN.
R_FB
I
1
Programmable strobe select
TxCLK OUT+
O
1
Positive LVDS differential clock output.
TxCLK OUT-
O
1
Negative LVDS differential clock output.
PWR DOWN
I
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down.
Vcc
I
3
Power supply pins for TTL inputs.
GND
I
4
Ground pins for TTL inputs.
PLL Vcc
I
1
Power supply pin for PLL.
PLL GND
I
2
Ground pins for PLL.
LVDS Vcc
I
1
Power supply pin for LVDS outputs.
LVDS GND
I
3
Ground pins for LVDS outputs.
DS90C385SLC SLC64A Package Pin Description-FPD Link Transmitter
Pin Name
I/O
No.
Description
TxIN
I
28
TTL level input.
TxOUT+
O
4
Positive LVDS differentiaI data output.
TxOUT-
O
4
Negative LVDS differential data output.
TxCLKIN
I
1
TTL Ievel clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
R_FB
I
1
Programmable strobe select. HIGH = rising edge, LOW = falling edge.
TxCLK OUT+
O
1
Positive LVDS differential clock output.
TxCLK OUT-
O
1
Negative LVDS differential clock output.
PWR DOWN
I
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low
current at power down.
Vcc
I
3
Power supply pins for TTL inputs.
GND
I
5
Ground pins for TTL inputs.
PLL Vcc
I
1
Power supply pin for PLL.
PLL GND
I
2
Ground pins for PLL.
LVDS Vcc
I
2
Power supply pin for LVDS outputs.
LVDS GND
I
4
Ground pins for LVDS outputs.
NC
6
Pins not connected.
Summary of Contents for HPT-4205
Page 1: ...42 PLASMA TV Built in Tuner SERVICE MANUAL...
Page 56: ...54 Plasma TV Service Manual 14 03 2005 15 CIRCUIT DIAGRAMS...
Page 57: ...55 Plasma TV Service Manual 14 03 2005...
Page 58: ...56 Plasma TV Service Manual 14 03 2005...
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