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Plasma TV Service Manual
14/03/2005
User programmable sharpness control
Detection of copy-protected signals according to the macrovision standard, indicating level of
protection
Independent gain and offset adjustment for raw data path.
Component video processing
RGB component inputs
Y-P
B
-P
R
component inputs
Fast blanking between CVBS and synchronous component inputs
Digital RGB to Y-C
B
-C
R
matrix.
Video scaler
Horizontal and vertical downscaling and upscaling to randomly sized windows
Horizontal and vertical scaling range: variable zoom to 1/64 (icon) (note: H and V zoom are restricted
by the transfer data rates)
Anti-alias and accumulating filter for horizontal scaling
Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase
accuracy)
Horizontal phase correct up and downscaling for improved signal quality of scaled data, especially for
compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width)
Two independent programming sets for scaler part, to define two
ranges
per field or sequences over
frames
Fieldwise switching between decoder part and expansion port (X-port) input
Brightness, contrast and saturation controls for scaled outputs.
Vertical Blanking Interval (VBI) data decoder and slicer
Versatile VBI-data decoder, slicer, clock regeneration and byte synchronization e.g. for World
Standard Teletext (WST), North-American Broadcast Text System (NABTS), close caption, Wide
Screen Signaling (WSS) etc.
Audio clock generation
Generation of a field-locked audio master clock to support a constant number of audio clocks per
video field
Generation of an audio serial and left/right (channel)
Digital I/O interfaces
Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status
information supporting RTC level 3.1 (refer to document
RTC Functional Specification
for details)
Bidirectional expansion port (X-port) with half duplex functionality (D1), 8-bit Y-C
B
-C
R
Output from decoder part, real-time and unscaled
Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible)
Video image port (I-port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own
clock), or slave mode (external clock), with auxiliary timing and handshake signals
Discontinuous data streams supported
32-word ´ 4-byte FIFO register for video output data
28-word ´ 4-byte FIFO register for decoded VBI-data output
Scaled 4 :2 :2, 4 :1 :1, 4 :2 :0, 4 :1 :0 Y-C
B
-C
R
output
Scaled 8-bit luminance only and raw CVBS data output
Sliced, decoded VBI-data output.
Miscellaneous
Power-on control
5 V tolerant digital inputs and I/O ports
Software controlled power saving standby modes supported
Programming via serial I 2 C-bus, full read back ability by an external controller, bit rate up to 400
kbits/s
Boundary scan test circuit complies with the
IEEE Std. 1149.b1 - 1994
BGA156 package.
Summary of Contents for HPT-4205
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