28
Plasma TV Service Manual
14/03/2005
12.22.3. Pinning
SYMBOL
PIN
TYPE
DESCRIPTION
XTOUT
A2
O
crystal oscillator output signal; auxiliary signal
XTALO
A3
O
24.576 MHz (32.11 MHz) crystal oscillator output; not
connected if TTL clock input of XTALI is used
V
SS(xtal)
A4
P
ground for crystal oscillator
TDO
A5
O
test data output for boundary scan test; note 2
XRDY
A6
O
task flag or ready signal from scaler, controlled by XRQT
XCLK
A7
I/O
clock I/O expansion port
XPD0
A8
I/O
LSB of expansion port data
XPD2
A9
I/O
MSB - 5 of expansion port data
XPD4
A10
I/O
MSB - 3 of expansion port data
XPD6
A11
I/O
MSB - 1 of expansion port data
TEST1
A12
I/pu
do not connect, reserved for future extensions and for testing:
scan input
TEST2
A13
I/pu
do not connect, reserved for future extensions and for testing:
scan input
AI41
B1
I
analog input 41
TEST3
B2
O
do not connect, reserved for future extensions and for testing
V
DD(xtal)
B3
P
supply voltage for crystal oscillator
XTALI
B4
I
input terminal for 24.576 MHz (32.11 MHz) crystal oscillator
or connection of external oscillator with TTL compatible
square wave clock signal
TDI
B5
I/pu
test data input for boundary scan test; note 2
TCK
B6
I/pu
test clock for boundary scan test; note 2
XDQ
B7
I/O
data qualifier for expansion port
XPD1
B8
I/O
MSB - 6 of expansion port data
XPD3
B9
I/O
MSB - 4 of expansion port data
XPD5
B10
I/O
MSB - 2 of expansion port data
XTRI
B11
I
X-port output control signal, affects all X-port pins (XPD7 to
XPD0, XRH, XRV, XDQ and XCLK), enable and active
polarity is under software control (bits XPE in subaddress
83H)
TEST4
B12
O
do not connect, reserved for future extensions and for testing:
scan output
TEST5
B13
NC
do not connect, reserved for future extensions and for testing
TEST6
B14
NC
do not connect, reserved for future extensions and for testing
VSSA4
C1
P
ground for analog inputs AI4x
AGND
C2
P
analog ground
TEST7
C3
NC
do not connect, reserved for future extensions and for testing
TEST8
C4
NC
do not connect, reserved for future extensions and for testing
V
DDD1
C5
P
digital supply voltage 1 (peripheral cells)
TRST
C6
I/pu
test reset input (active LOW), for boundary scan test (with
internal pull-up); notes 2, 3 and 4
XRH
C7
I/O
horizontal reference I/O expansion port
V
DDD2
C8
P
digital supply voltage 2 (core)
V
DDD3
C9
P
digital supply voltage 3 (peripheral cells)
V
DDD4
C10
P
digital supply voltage 4 (core)
XPD7
C11
I/O
MSB of expansion port data
TEST9
C12
NC
do not connect, reserved for future extensions and for testing
TEST10
C13
NC
do not connect, reserved for future extensions and for testing
TEST11
C14
I/pu
do not connect, reserved for future extensions and for testing:
scan input
AI43
D1
I
analog input 43
AI42
D2
I
analog input 42
AI4D
D3
I
differential input for ADC channel 4 (pins AI41 to AI44)
V
DDA4
D4
P
analog supply voltage for analog inputs AI4x (3.3 V)
V
SSD1
D5
P
digital ground 1 (peripheral cells)
TMS
D6
I/pu
test mode select input for boundary scan test or scan test;
note 2
V
SSD2
D7
P
digital ground 2 (core; substrate connection)
XRV
D8
I/O
vertical reference I/O expansion port
Summary of Contents for HPT-4205
Page 1: ...42 PLASMA TV Built in Tuner SERVICE MANUAL...
Page 56: ...54 Plasma TV Service Manual 14 03 2005 15 CIRCUIT DIAGRAMS...
Page 57: ...55 Plasma TV Service Manual 14 03 2005...
Page 58: ...56 Plasma TV Service Manual 14 03 2005...
Page 59: ...57 Plasma TV Service Manual 14 03 2005...
Page 60: ...58 Plasma TV Service Manual 14 03 2005...
Page 61: ...59 Plasma TV Service Manual 14 03 2005...
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