A1-2
G8 CPCI Enclosure User’s Guide
Appendix 1 - Technical Reference
PCI Bus transaction
FRAME_
Cycle Frame
control signals
TRDY_
Target Ready
IRDY_
Initiator Ready
STOP_
Target/Initiator transac
tion stop bit
IDSEL
Initialization Device
Select
LOCK_
Resource Lock bit
DEVSEL_
Device Select
PCI bus error
PERR_
Data Parity Error
reporting signals
SERR_
System Error
PCI bus speed signals
M66EN
66MHz bus enable
PCI bus clock
CLK0
System Management
IPMB_SCL
Bus
IPMB_SDA
IPMB_PWR
64-bit Extension
REQ64_
Request 64-bit Transfer
Signals
ACK 64_
Acknowledge 64-bit Transfer
JTAG/Boundary
TCK
Test Clock
Scan Signals
TDI
Test Input
TDO
Test Output
TMS
Test Mode Select
TRST_
Test Reset
IDE Interrupts
INTP
Primary Interrupt
(IRQ14)
INTS Secondary Interrupt
IRQ15)
Hot Swap compatible
ENUM_
System Enumeration
signals
BD_SEL_
Board Slot Control
HEALTHY_
Board Healthy
Summary of Contents for G8
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