Interrupt and DMA Assignments
Most IRQ assignments are dynamic because of Plug-and-Play and PCI configuration. However, some are
fixed based on legacy requirements, as shown in the table below. Because the SurePOS 500-XX3 design will
make use of the APIC interrupt controller in the ICH4, there will be 20 interrupts instead of 16 as we had in
the previous designs. The legacy ISA interrupts are the same from 0 - 15, and interrupts 16-19 correspond
to the PCI interrupts INTA, INTB, INTC, and INTD. Thus PCI devices no longer need to take an ISA interrupt
with the APIC design.
IRQ Number
Resource
Notes...
0
System Timer
NS (Not Sharable)
1 PS2
Keyboard
NS
2 Cascade
NS
6
Floppy Drive
NS, available if floppy not attached or
enabled
8 RTC NS
12
Mouse
NS, available is mouse not attached or
enabled
13 Floating
Point
NS
14 HDD
controller
NS
Below is a list of other resources that will be configured to any available interrupt:
Resource Notes
Serial A
Relocate and can be Disabled
Serial B
Relocate and can be Disabled
LPT1
Relocate and can be Disabled
Ethernet
Relocate and can be Disabled
PCMCIA
Relocate and can be Disabled
Audio
Relocate and can be Disabled
USB
Relocate and can be Disabled
MSR
Relocate and can be Disabled
VFD
Relocate and can be Disabled
Serial C
Relocate and can be Disabled
SurePOS 500 Model XX3 Technical Reference, v 1.3 Page 41 of
81
Summary of Contents for 4840-563
Page 15: ...Chapter 3 Architectural Overview SurePOS 500 Model XX3 Technical Reference v 1 3 Page 15 of 81...
Page 17: ...Main Board Block Diagram SurePOS 500 Model XX3 Technical Reference v 1 3 Page 17 of 81...
Page 80: ...SurePOS 500 Model XX3 Technical Reference v 1 3 Page 80 of 81...
Page 81: ...END OF DOCUMENT SurePOS 500 Model XX3 Technical Reference v 1 3 Page 81 of 81...