IBM System x3950 M2 and x3850 M2 Technical Introduction
19
Figure 10 compares the layout of the Tigerton
dual-core and quad-core processors.
Figure 10 Comparing the dual-core and quad-core Tigerton
Key features of the processors used in the x3850 M2 and x3950 M2 include:
Models with dual-core or quad-core processors
The Tigerton dual-core processors are a concept similar to a two-way SMP system except
that the two processors, or
cores
, are integrated into one silicon die. This brings the
benefits of two-way SMP with less power consumption and faster data throughput
between the two cores. To keep power consumption down, the resulting core frequency is
lower, but the additional processing capacity means an overall gain in performance.
The Tigerton
quad-core processors add two more cores onto the same die.
Hyper-Threading Technology is not supported.
Each core has separate L1 instruction and data caches, as well as separate execution
units (integer, floating point, and so on), registers, issue ports, and pipelines for each core.
A multi-core processor achieves more parallelism than Hyper-Threading Technology,
because these resources are not shared between the two cores.
With double and quadruple the number of cores for the same number of sockets, it is even
more important that the memory subsystem is able to meet the demand for data
throughput. The 34.1 GBps peak throughput of the x3850 M2 and x3950 M2 eX4
Architecture with four memory cards is well-suited to dual-core and quad-core processors.
1066 MHz front-side bus
The Tigerton Xeon MP uses two 266 MHz clocks, out of phase with each other by 90°, and
using both edges of each clock to transmit data. This is shown in Figure 11.
Figure 11 Quad-pumped front-side bus
L1 Instruct
Cache
L1 Data
Cache
L2
Cache
Quad-core Xeon E7300 series
(Code name: Tigerton)
L2
Cache
L1
Instruct
Cache
L1
Data
Cache
Processor
Core
L2
Cache
Dual-core Xeon E7210
(Code name: Tigerton)
L1
Instruct
Cache
L1
Data
Cache
Processor
Core
L2
Cache
Processor
Core
L1 Instruct
Cache
L1 Data
Cache
L1 Instruct
Cache
L1 Data
Cache
L1 Instruct
Cache
L1 Data
Cache
Processor
Core
Processor
Core
Processor
Core
266 MHz clock A
266 MHz clock B
