Leadership enterprise server with significantly lower cost of ownership in a highly available and
expandable, rack-dense, 2U dual-socket server
Please see the Legal Information section for important notices and information.
5
cache is dynamically allocated between the cores as needed. The multiple cores appear to
software as multiple physical processors. The two-core processors offer considerably higher
performance than a same-speed Xeon processor with a single core. Likewise, four-core
processors offer considerably higher performance than a same-speed Xeon processor with dual
cores.
Turbo Boost Technology
dynamically turns off unused processor cores and increases the clock
speed of the cores in use, by up to two model frequencies. For example, with
three
cores active,
a
2.26GH
z processor can run the cores at
2.4GHz
. With only
one
or
two
cores active, the same
processor can run those cores at
2.53GHz
. Similarly, a
2.93GHz
processor can run at
3.06GHz
or even
3.33GHz
. When the cores are needed again, they are dynamically turned back on and
the processor frequency is adjusted accordingly.
Intel
Extended Memory 64 Technology (EM64T)
64-bit extensions allow the Xeon processor to
use large memory addressing when running with a 64-bit operating system. This in turn lets
individual software processes directly access more than 4GB of RAM, which was the limit of 32-
bit addressing. This can result in much higher performance for certain kinds of programs, such as
database management and CAD. Additional registers and instructions (SSE3) can further boost
performance for applications written to use them. Contact your software provider to determine
their software support for EM64T.
Intelligent Power Capability
powers individual processor elements on and off as needed, to
reduce power draw.
Execute Disable Bit
functionality can help prevent certain classes of malicious buffer overflow
attacks when combined with a supporting operating system.
DDR-3 Registered Memory with Chipkill ECC Protection
The x3650 M2 ships with registered double data rate III (DDR-3) memory and provides Active
Memory features, including advanced
Chipkill
memory protection (optionally), for
up to 16X
better error correction than standard ECC memory. In addition to offering better performance than
DDR-2 or fully-buffered memory, DDR-3 memory also uses less energy. DDR-2 memory already
offered up to 37% lower energy use than fully buffered memory. Now, a generation later, DDR-3
memory is even more efficient, using
22% less
energy
than DDR-2 memory.
The x3650 M2 supports up to
128GB
of memory in
sixteen
DIMM slots. Redesign in the
architecture of the Xeon 5500 series processors bring radical changes in the way memory works
in these servers. For example, the Xeon 5500 series processor
integrates the memory
controller inside the processor
, resulting in two memory controllers in a 2-socket system. Each
memory controller has three memory channels. Depending on the type of memory, population of
memory, and processor model, the memory may be clocked at
1333MHz
,
1066MHz
or
800MHz
.
Note:
If only one processor is installed, only the first eight DIMM slots can be used. Adding a
second processor not only doubles the amount of memory available for use, but also doubles the
number of memory controllers, thus doubling the system memory bandwidth. If you add a second
processor, but no additional memory for the second processor, the second processor has to
access the memory from the first processor “remotely,” resulting in longer latencies and lower
performance. The latency to access remote memory is almost
75% higher
than local memory
access. So, the goal should be to always populate both processors with memory.
The
X55
xx models support up to 1333MHz memory clock speed, while the
E55x
x-and-up and
L55x
x-and-up models support up to 1066MHz clock speed, and the
E550
x models support
Ch1
Ch0
Ch2
Ch1
Ch0
Ch2
Xeon 5500
Processor 0
Memory Controller
7
4
6
3
8
5
Xeon 5500
Processor 1
14
11
QPI
Memory Controller
1
2
15
12
16
13
9
10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
1-16: DIMM population sequence;
D1-D16: DIMM slot assignments