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IBM
Eserver
xSeries 455 Planning and Installation Guide
unmatched “economies of scale” and new levels of server availability and
performance.
Much of the Enterprise X-Architecture offering is delivered through
IBM-developed core logic. IBM has more proven product technology and
expertise in designing core logic than anyone else in the industry. The IBM XA-32
and XA-64 families of chipsets for 32-bit and 64-bit industry-standard servers
contain advanced core logic, which is the heart of a computer system. Core logic
determines how the various parts of a system (processors, system cache, main
memory, I/O, etc.) interact. These new chipsets bring to the next generation of
industry-standard servers key advantages, including modular system nodes,
system partitioning, high-performance clustering, and high-speed remote PCI-X
I/O support.
The Enterprise X-Architecture paradigm sets IBM xSeries servers apart in the
industry while maintaining the advantages of compliance with industry standards
for processors, memory, I/O, storage and software. Enterprise X-Architecture
also establishes a revolutionary new economic model for servers through its
flexible modular design. The x455 Enterprise X-Architecture-based server allows
customers to XpandOnDemand, the ability to grow when you need to, using the
existing infrastructure.
More Information on Enterprise X-Architecture technology can be found at:
http://www.pc.ibm.com/us/eserver/xseries/xarchitecture/enterprise
1.12.1 NUMA architecture
SMP designs are currently being challenged by the demand for additional Intel
processors within a single system. In SMP, CPUs have equal access to a single
shared memory controller and memory space. Because processor speed has
dramatically increased to be much faster than memory, for most CPU intensive
workloads the single front-side bus and single memory controller are often a
bottleneck, resulting in excessive queuing delays and long memory latencies
when under heavy load.
Processor instruction and data caches have been introduced to help reduce the
likelihood of a memory controller bottleneck. A performance boost is often
obtained from using large caches because of two reasons:
Caches have lower latency and faster access time than a memory access.
Because a cache can be accessed more quickly than memory, the processor
waits less time before receiving a response from a request.
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