IBM E850C Technical Overview And Introduction Download

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Chapter 2. Architecture and technical overview

By adopting this architecture for the memory DIMMs, several decisions and processes
regarding memory optimizations are run internally into the CDIMM. This technique saves
bandwidth and allows for faster processor-to-memory communications. It also allows for a more
robust RAS. For more information, see Chapter 4, “Reliability, availability, and serviceability” on
page 101.

2.5.1 CDIMM design

The CDIMMs exist in two different form factors:

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A 152 SDRAM design that is named the

Tall CDIMM

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An 80 SDRAM design that is named the

Short CDIMM

Each design is composed of multiple 4 GB SDRAM devices depending on its total capacity.
The CDIMMs for the Power E850C server are short CDIMMs. Tall CDIMMs from other
Enterprise Systems such as the Power E870 and Power E880 are not compatible with the
Power E850C server.

The Power E850C supports CDIMMs in 16 GB, 32 GB, 64 GB, and 128 GB capacities. Each
CDIMM incorporates a 16 MB Memory Buffer, also known as

L4 cache

. The L4 cache is built

on eDRAM technology (same as the L3 cache), which has a lower latency than regular
SRAM. Each CDIMM has 16 MB of L4 cache and a fully populated Power E850C server with
four processor modules has 512 MB of L4 Cache. The L4 Cache performs several functions
that have direct impact on performance and bring a series of benefits for the Power E850C
server:

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Reduces energy consumption by reducing the number of memory requests.

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Increases memory write performance by acting as a cache and by grouping several
random writes into larger transactions.

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Partial write operations that target the same cache block are gathered within the L4 cache
before being written to memory, becoming a single write operation.

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Reduces latency on memory access. Memory access for cached blocks has up to 55%
lower latency than non-cached blocks.

2.5.2 Memory placement rules

For the Power E850C, each memory feature code provides a single CDIMM. These memory
features must be ordered in pairs of the same memory feature. Both CDIMMs of a CDIMM
pair must be installed in CDIMM slots supporting one processor. Different size pairs can be
mixed on the same processor. However, for optimal performance ensure that all CDIMM pairs
that are connected to a processor are of the same capacity. Also, ensure that the number of
memory CDIMM pairs is the same on each processor module of a system.

System performance improves as more CDIMM pairs match. System performance also
improves as more CDIMM slots are filled, because this configuration increases the memory
bandwidth available. Therefore, if 256 GB of memory is required, using sixteen 16 GB
CDIMMs would offer better performance than using eight 32 GB CDIMMs. This configuration
allows memory access in a consistent manner and typically results in the best possible
performance for your system. You should account for any plans for future memory upgrades
when you decide which memory feature size to use at the time of the initial system order.