IBM F16 User Manual Download

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thermometers, and miscellaneous I/O are handled by the I2C bus of the CPU. The
CPU is the only I2C bus master in the system. The RS232 port and drivers,
Ethernet MAC/PHY, and LEDs are external components to the CPU. An RJ45
connector provides Ethernet connection to external systems. The DB9 RS232 is a
ribbon-cable connection through the on-board 10-pin header.

Bus operations

The interface between the embedded processor, the ASICs, and the 10BASE-T or
100BASE-T Ethernet MAC is implemented by using a PCI bus. All PCI devices on
the bus are PCI Revision 2.2 compliant. The PCI bus interface operates at 32-bit,
up to 33 MHz and has a worldwide even parity bit. A slave-only PCI interface is
provided by each ASIC to allow the processor to program various registers, routing
tables, and so on within the chip. An external PCI bus arbiter enables the Ethernet
device to be a bus master.

The local bus, a 32-bit multiplexed burst bus, provides the interface between the
system memory and the I/O. Because the integrated EDO memory controller on the
CPU allows only direct control for DRAM, SRAM, ROM, and Flash memory, the
external CPLD controller is included to provide SDRAM controller functionality.

The I2C bus provides peripheral I/O control for the LEDs, the thermometers, and
general I/O functions. The 80960VH CPU serves as the master on the I2C bus.

Each Bloom ASIC is an eight-port Fibre Channel switch controller. There are two
Bloom ASICs to support up to 16 ports. The communication between ASICs is over
a proprietary 10-bit wide SSTL2 bus running at 106.25 MHz. An SSTL2 bus is also
used between the Bloom ASICs and the SERDES.

Memory

The system design uses three types of memory devices:

DRAM

Flash File

Boot Flash

Two on-board SDRAM chips provide up to 16 MB for system memory. Two
additional SDRAM chips provide data parity. The printed circuit board (PCB)
SDRAM footprint is designed to be compatible with 64 MB, 128 MB, and 256 MB
devices. An external CPLD device added to the local bus provides control functions
for the 80960VH processor.

The system provides 4 MB of on-board redundant Flash File memory for software
and data storage. The Boot Flash is an 8-bit Flash device socket that is used only
for system start. The Boot Flash device contains a block area for startup code
protection. The PLCC32 socket supports 3.3 V Boot Flash memory up to 512 KB.

Central memory:

As with the 2019 series of switches and the 3534 switch, the

2109 Model F16 is based on a central memory architecture. In this architecture, a
set of buffers in the central memory is assigned to each port to be used for receipt
of frames. As an ASIC port receives and validates a frame, it stores the frame in
one of its receive buffers in the central memory and forwards a routing request (a
Put message) to the appropriate destination ports. When a destination port is
capable of transmitting the frame, it reads the frame contents from central memory
and forwards the frame to its transmit interface. It does not wait for the frame to be
written in memory, unless the port is busy. After it removes an entry for a frame
from its internal transmit queue in preparation for transmitting a frame, the

Chapter 1. Introduction