© Copyright IBM Corp. 2005, 2006. All rights reserved.
9
Chapter 2.
Architecture and technical
overview
This chapter discusses the overall system architecture represented by Figure 2-1. We
describe the major components of this diagram in the following sections. The bandwidths
provided throughout this section are theoretical maximums provided for your reference. We
recommend that you use production workloads to obtain your real-world performance
measurements.
Figure 2-1 IntelliStation POWER 285 logical architecture
2
Enhanced
I/O Controller
GX+
700
MHz
Service Processor
System Ports
P1-T1 T2
HMC ports
P1-C7-T1 T2
Rack Indicator Light
cable port P1-T9
CoD key card
buzz interface
USB ports
P1-T7 T8
Ethernet ports
P1-T5 T6
USB
32-bit
Dual 1GB
Ethernet
64-bit
P
C
I-
X
sl
ot 1
, 64
-b
it,
13
3 M
H
z,
3
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lts
P
C
I-
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sl
ot 2
, 32
-b
it,
66
M
H
z,
3
.3 v
o
lts
P
C
I-
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sl
ot 3
, 32
-b
it,
66
M
H
z,
3
.3 v
o
lts
P
C
I-
X
sl
ot 4
, 64
-b
it,
26
6 M
H
z,
3
.3 v
o
lts
P
C
I-
X
sl
ot 5
, 64
-b
it,
13
3 M
H
z,
3
.3 v
o
lts
Short
Long
Long
Short
Short
PCI-X to PCI-X
bridge 0
133
MHz
33
MHz
PCI-X to PCI-X
bridge 3
IDE
controller
133 MHz 64-bit
Dual SCSI
Ultra320 64-bit
4-pack disk drive backplane
P3-T14-L15-L0
Tape drive
P4-D1
Optional media backplane
Slim-line media device
Slim-line media device
Operator panel
P1-C1
C2
C3
C4
C5
P3
-D
1
P3
-D
2
P3
-D
3
P3
-D
4
P
3-
T
11-
L8-
L0
P
3-
T
11-
L5-
L0
P
3-
T
11-
L4-
L0
P
3-
T
11-
L3-
L0
66 MHz
32-bit
PO
W
E
R
5+
cor
e
2.
1 G
H
z
PO
W
E
R
5+
cor
e
2.
1 G
H
z
PO
W
E
R
5+
cor
e
2.
1 G
H
z
PO
W
E
R
5+
cor
e
2.
1 G
H
z
1.
9 M
B
S
har
ed
L2
c
ac
he
L3
Ct
rl
Me
m
Ct
rl
DCM
E
n
ha
n
c
ed
distr
ib
u
ted
sw
it
ch
SMI-II
SMI-II
1056 MHz
2x8 B for read
2x8 B for write
D
IMM C
X
J
X
X
“
A
x”
D
IMM C
X
J
X
X
“
A
x”
D
IMM C
X
J
X
X
“
A
x”
D
IMM C
X
J
X
X
“
A
x”
D
IMM C
X
J
X
X
“
A
x”
D
IMM C
X
J
X
X
“
A
x”
D
IMM C
X
J
X
X
“
A
x”
D
IMM C
X
J
X
X
“
A
x”
2x8 B
@528 MHz
36
MB
L3
cache
2x16 B
@1.05 GHz
P
C
I-
X
sl
ot 6
, 64
-b
it,
13
3 M
H
z,
3
.3 v
o
lts
Long
C6
RAID enablement
card
