IBM Power 595 Technical Overview And Introduction Download

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Chapter 4. Continuous availability and manageability

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purged, and the line is dynamically deleted (removed from further use). The state of L3 cache
line delete is maintained in a

deallocation record

, so line delete persists through system IPL.

This ensures that cache lines

varied offline

by the server can remain offline if the server is

rebooted. These

error prone

lines cannot then cause system operational problems. A server

can dynamically delete up to 10 cache lines in a POWER5 processor-based server and up to
14 cache lines in POWER6 processor-based models. Deletion of this many cache lines are
unlikely to adversely affect server performance. If this total is reached, the L3 cache is marked
for persistent deconfiguration on subsequent system reboots until repaired.

Furthermore, for POWER6 processor-based servers, the L3 cache includes a purge delete
mechanism for cache errors that cannot be corrected by ECC. For unmodified data, purging
the cache and deleting the line ensures that the data is read into a different cache line on
reload, thus providing good data to the cache, preventing reoccurrence of the error, and
avoiding an outage. For an uncorrectable error (UE) on modified data, the data is written to
memory and marked as a SUE. Again, purging the cache and deleting the line allows
avoidance of another UE.

In addition, POWER6 process-based servers introduce a hardware assisted cache memory
scrubbing feature where all the L3 cache memory is periodically addressed and any address
with an ECC error is rewritten with the faulty data corrected. In this way, soft errors are
automatically removed from L3 cache memory, decreasing the chances of encountering
multi-bit memory errors.

4.2.4 The input output subsystem

All IBM POWER6 processor-based servers use a unique

distributed switch

topology

providing high bandwidth data busses for fast efficient operation. The high-end Power 595
server uses an 8-core building block. System interconnects scale with processor speed.
Intra-MCM and Inter-MCM busses at half processor speed. Data movement on the fabric is
protected by a full ECC strategy. The GX+ bus is the primary I/O connection path and
operates at half the processor speed.

In this system topology, every node has a direct connection to every other node, improving
bandwidth, reducing latency, and allowing for new availability options when compared to
earlier IBM offerings. Offering further improvements that enhance the value of the
simultaneous multithreading processor cores, these servers deliver exceptional performance
in both transaction processing and numeric-intensive applications. The result is a higher level
of SMP scaling. IBM POWER6 processor servers can support up to 64 physical processor
cores.

I/O drawer and tower redundant connections and concurrent repair

Power System servers support a variety integrated I/O devices (disk drives, PCI cards). The
standard server I/O capacity can be significantly expanded in the rack mounted offerings by
attaching optional I/O drawers or I/O towers using IBM RIO-2 busses, or on POWER6
processor offerings, a 12x channel adapter for optional 12x channel I/O drawers. A remote I/O
(RIO) loop or 12x cable loop includes two separate cables providing highspeed attachment. If
an I/O cable becomes inoperative during normal system operation, the system can
automatically reconfigure to use the second cable for all data transmission until a repair can
be made. Selected servers also include facilities for I/O drawer or tower concurrent additions
(while the system continues to operate) and allow the drawer or tower to be varied on or
off-line. Using these features, a failure in an I/O drawer or tower that is configured for
availability (I/O devices accessed through the drawer must not be defined as

required

for a

partition boot or, for IBM i partitions, ring level or tower level mirroring has been implemented)
can be repaired while the main server continues to operate.