IBM Power 595 Technical Overview And Introduction Download

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IBM Power 595 Technical Overview and Introduction

manager and ML2 layer is the agent or the manageable unit. ML3 layer functions submit
transactions that are executed by the ML2 layer.

The System Controllers’s scope is, as reported before, to manage one system consisting of
one or more subsystems such as processor books (called

nodes

), I/O drawers and the power

control subsystem. The system control structure (SCS) is implemented with complete
redundancy. This includes the service processors, interfaces and VPD and smart chip
modules.

The SC communicates exclusively via TCP/IP over Ethernet through the Bulk Power Hub
(BPH), is implemented as a service processor embedded controller. Upstream it
communicates with the HMC, downstream it communicates with the processor book
subsystem controllers called Node Controllers (NC). The NC is also implemented as a
service processor embedded controller.

Each processor book cage contains two embedded controllers called Node Controllers
(NCs), which interface with all of the logic in the corresponding book. Two NCs are used for
each processor book to avoid any single point of failure. The controllers operate in master and
subordinate configuration. At any given time, one controller performs the master role while the
other controller operates in standby mode, ready to take over the master's responsibilities if
the master fails. Node controller boot over the network from System Controller.

Referring again to Figure 2-7 on page 44, in addition to its intra-cage control scope, the NC
interfaces with a higher-level system-control entity as the system controller (SC). The SC
operates in the ML3 domain of the system and is the point of system aggregation for the
multiple processor books. The SCS provides system initialization and error reporting and
facilitates service. The design goal for the Power systems function split is that every Node
Controller (ML2 controller) controls its node as self-contained as possible, such as initializes
all HW components within the node in an autonomic way.

The SC (ML3 controller) is then responsible for all system-wide tasks, including NC node
management, and the communication with HMC and hypervisor. This design approach yields
maximum parallelism of node specific functions and optimizes performance of critical system
functions, such as system IPL and system dump, while minimizing external impacts to HMC
and hypervisor.

Further to the right in Figure 2-7 on page 44, the downstream fan-out into the sensors and
effectors is shown. A serial link, the FRU Support interface (FSI), is used to reach the
endpoint controls.

The endpoints are called Common FRU Access Macro (CFAM). CFAMs are integrated in the
microprocessors and all I/O ASICs. CFAMs support a variety of control interfaces such as
JTAG, UART, I2C, and GPIO.

Also what it shown is a link called the Processor Support Interface (PSI). This interface is new
in Power Systems. It is used for high-speed communication between the service subsystem
and the host firmware subsystem. Each CEC node has 4 PSI links associated with it, one
from each processor chip.

The BPH is a VLAN capable switch, that is part of the BPA. All SCs and NCs and the HMC
plug into that switch. The VLAN capability allows a single physical wire to act as separate
virtual LAN connections. The SC and BPC will make use of this functionality.

The switch is controlled (programmed) by the BPC firmware.